DLA DSCC-VID-V62 03610 REV B-2012 MICROCIRCUIT DIGITAL CMOS DIGITAL SIGNAL PROCESSOR MONOLITHIC SILICON.pdf

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1、 REVISIONSLTR DESCRIPTION DATE (YY-MM-DD) APPROVEDA Correct lead finish on last page. Update boilerplate. - CFS 05-11-01 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 12-03-22 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MA

2、RITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV B B B B B B B B B PAGE 40 41 42 43 44 45 46 47 48 REV B B B B B B B B B B B B B B B B B B B B B B PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES REV B B B B B

3、B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Thanh V. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Thanh V. Nguyen TITLE MICROCIRCUIT, DIGITAL, CMOS, DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON YY

4、-MM-DD 02-12-18 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03610 REV B PAGE 1 OF 51 AMSC N/A 5962-V040-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16

5、236 DWG NO. V62/03610 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance digital signal processor microcircuit, with an operating temperature range of -40C to +100C for device type 01 and -55C to +125C for device type 02 as shown in 1.2.1 below. 1.

6、2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03610 - 01 X E Drawing Device type Case outline Lead finish nu

7、mber (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 320VC33-EP Digital signal processor 02 320VC33-EP Digital signal processor 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style

8、 X 144 MS-026 Plastic quad flatpack Y 144 Ceramic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z O

9、ther Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03610 REV B PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (DVDD) -0.3 V to +4.0 V 2/ Supply vol

10、tage range (CVDD) -0.3 V to +2.4 V 2/ Input voltage range (VI). -1.0 V to +4.6 V 3/ Output voltage range (VO) . -0.3 V to +4.6 V Continuous power dissipation (worst case) (PD) . 500 mW 4/ Storage temperature range (TSTG) -55C to +150C 5/ Case operating temperature range (TC): Device type 01 . -40C t

11、o +100C Device type 02 . -55C to +125C 1.4 Recommended operating conditions. 2/ 6/ 7/ 8/ Supply voltage range for the core CPU (CVDD) . 1.71 V to 1.89 V 9/ Supply voltage range for the I/O pins (DVDD) 3.0 V to 3.6 V 10/ Supply ground (VSS) 0.0 V High level input voltage range (VIH) . 0.7 x DVDDto DV

12、DD+ 0.3 V 3/ Low level input voltage range (VIL) -0.3 V to 0.3 x DVDD3/ Maximum high level output current (IOH) . 4.0 mA Maximum low level output current (IOL) . 4.0 mA Case operating temperature range (TC): Device type 01 . -40C to +100C Device type 02 . -55C to +125C Maximum capacitive load per ou

13、tput pin (CL) 30 pF 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

14、implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltage values are with respect to VSS. 3/ Absolute dc input level should not exceed the DVDDor VSSsupply rails by more than 0.3 V. An instantaneous low current pulse of 2 ns, 10 mA, and

15、 1 V amplitude is permissable. 4/ Actual operating power is much lower. This value was obtained under specially produced worst-case test conditions for the device, which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern

16、 to the external data and address buses at the maximum possible rate with a capacitive load of 30 pF. See normal (IDD) current specification in table I herein. 5/ Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall d

17、evice life. 6/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 7/ All inputs and I/O pins are configured as inputs. 8/ All

18、inputs and I/O pins use a Schmidt hysteresis inputs except SHZ and D0 D31. Hysteresis is approximately 10% of DVDDand is centered at 0.5 x DVDD. 9/ CVDDshould not exceed DVDDby more than 0.7 V. (Use a Schottky clamp diode between these supplies.) 10/ DVDDshould not exceed CVDDby more than 2.5 V. Pro

19、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03610 REV B PAGE 4 2. APPLICABLE DOCUMENTS THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE) IEEE Standard

20、1149.1 - IEEE Standard Test Access Port and Boundary Scan Architecture. (Copies of these documents are available online at http:/www.ieee.org or from the IEEE Service Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 088551331. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and

21、 Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked w

22、ith the manufacturers part number as shown in 6.4 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) ab

23、ove. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified here

24、in. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Functional block diagram. The functional block diagram shall be as shown in figure 2. 3.5.3 Terminal connections. The terminal connections shall be as shown in figure 3. 3.5.4 Test circuit and

25、 timing waveforms. The test circuit and timing waveforms shall be as shown in figure 4. 3.5.5 Boundary scan instruction code. The boundary scan instruction code shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SU

26、PPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03610 REV B PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ 3/ 3.0 V DVDD 3.6 V 1.71 V CVDD 1.89 V unless otherwise specified Temperature, TC Device type Limits Unit Min Max High level o

27、utput voltage VOHDVDD= Min, IOH= Max 25C, -40C to 100C 01 2.4 V 25C, -55C to 125C 02 2.4 Low level output voltage VOLDVDD= Min, IOL= Max 25C, -40C to 100C 01 0.4 V 25C, -55C to 125C 02 0.4 High impedance current IZDVDD= Max 25C All -5.0 +5.0 A Input current IIVI= VSSto DVDD 25C All -5.0 +5.0 A Input

28、 current (with internal pullup) IIPUInputs with internal pullups 4/ 25C, -40C to 100C 01 -600 10 A 25C, -55C to 125C 02 -600 10 Input current (with internal pulldown) IIPDInputs with internal pulldowns 4/ 25C, -40C to 100C 01 600 -10 A 25C, -55C to 125C 02 600 -10 Input current (with bus keeper) pul

29、lup 5/ IBKUBus keeper opposes until conditions match 25C, -40C to 100C 01 -600 10 A 25C, -55C to 125C 02 -600 10 Input current (with bus keeper) pulldown 5/ IBKD25C, -40C to 100C 01 600 -10 A 25C, -55C to 125C 02 600 -10 Supply current, pins 6/ 7/ IDDDDVDD= Max, fX= 60 MHz 25C 01 120 mA DVDD= Max, f

30、X= 75 MHz 25C 02 260 Supply current, core CPU 6/ 7/ IDDCCVDD= Max, fX= 60 MHz 25C 01 80 mA CVDD= Max, fX= 75 MHz 25C 02 215 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO

31、SIZE A CODE IDENT NO. 16236 DWG NO. V62/03610 REV B PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ 3/ 3.0 V DVDD 3.6 V 1.71 V CVDD 1.89 V unless otherwise specified Temperature, TCDevice type Limits Unit Min Max IDLE2, Supply current, IDDDplus IDDCID

32、DPLL enabled, oscillator enabled 25C, -40C to 100C 01 2 typical mA 25C, -55C to 125C 02 2 typical PLL disabled, oscillator enabled 25C, -40C to 100C 01 500 typical A 25C, -55C to 125C 02 500 typical PLL disabled, oscillator disabled,FLCK = 0 25C, -40C to 100C 01 50 typical 25C, -55C to 125C 02 50 ty

33、pical Input capacitance 8/ CIAll inputs except XIN 25C All 10 pF XIN input 10 Output capacitance 8/ CO 25C All 10 pF Phase-locked loop characteristics using EXTCLK or on-chip crystal oscillator 9/ Frequency range, PLL input 8/ Fpllin 25C, -40C to 100C 01 5 15 MHz 25C, -55C to 125C 02 5 15 Frequency

34、range, PLL output 8/ Fpllout 25C, -40C to 100C 01 25 75 MHz 25C, -55C to 125C 02 25 75 PLL current, CVDDsupply 8/ Ipll 25C, -40C to 100C 01 2 mA 25C, -55C to 125C 02 2 PLL power, CVDDsupply 8/ Ppll 25C, -40C to 100C 01 5 mW 25C, -55C to 125C 02 5 PLL output duty cycle at H1 8/ PLLdc 25C, -40C to 100

35、C 01 45 55 % 25C, -55C to 125C 02 45 55 PLL output jitter, Fpllout= 25 MHz 8/ PLLJ 25C, -40C to 100C 01 400 ps 25C, -55C to 125C 02 400 PLL lock time in input cycles PLLLOCK 25C, -40C to 100C 01 1000 cycles25C, -55C to 125C 02 1000 See footnotes at end of table. Provided by IHSNot for ResaleNo repro

36、duction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03610 REV B PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ 3/ 3.0 V DVDD 3.6 V 1.71 V CVDD 1.89 V unle

37、ss otherwise specified Temperature, TCDevice type Limits Unit Min Max Circuit parameters for on-chip crystal oscillator 10/ Oscillator internal supply voltage VO See figure 4 25C, -40C to 100C 01 CVDDtypical V 25C, -55C to 125C 02 CVDD typical Fundamental mode frequency range 8/ FO 25C, -40C to 100C

38、 01 1 20 MHz 25C, -55C to 125C 02 1 20 DC bias point (input threshold) 8/ Vbias 25C, -40C to 100C 01 40 60 %VO 25C, -55C to 125C 02 40 60 Feedback resistance 8/ Rfbk 25C, -40C to 100C 01 100 500 k 25C, -55C to 125C 02 100 500 Small signal ac output impedance 8/ Rout 25C, -40C to 100C 01 250 1000 25C

39、, -55C to 125C 02 250 1000 The ac output voltage with test crystal 11/ Vxoutac 25C, -40C to 100C 01 85 typical %VO 25C, -55C to 125C 02 85 typical The ac input voltage with test crystal 11/ Vxinac 25C, -40C to 100C 01 85 typical %VO 25C, -55C to 125C 02 85 typical Vxin= Vxinh, Ixout= 0, FO= 0 (logic

40、 input) 8/ Vxoutl 25C, -40C to 100C 01 VSS-0.1 VSS+0.3 V 25C, -55C to 125C 02 VSS -0.1 VSS+0.3 Vxin= Vxinl, Ixout= 0, FO= 0 (logic input) 8/ Vxouth 25C, -40C to 100C 01 CVDD-0.3 CVDD+0.1 V 25C, -55C to 125C 02 CVDD -0.3 CVDD+0.1 When used for logic level input, oscillator enabled 8/ Vinl 25C, -40C t

41、o 100C 01 -0.3 0.2VO V 25C, -55C to 125C 02 -0.3 0.2VO When used for logic level input, oscillator enabled 8/ Vinh 25C, -40C to 100C 01 0.8VO DVDD+0.3 V 25C, -55C to 125C 02 0.8VO DVDD +0.3 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without li

42、cense from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03610 REV B PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ 3/ 3.0 V DVDD 3.6 V 1.71 V CVDD 1.89 V unless otherwise specified Temperature, TCDevi

43、ce type Limits Unit Min Max Circuit parameters for on-chip crystal oscillator - Continued 10/ When used for logic level input, oscillator disabled 8/ Vxinh See figure 4 25C, -40C to 100C 01 0.7 DVDDDVDD+0.3 V 25C, -55C to 125C 02 0.7 DVDDDVDD+0.3 XOUT internal load capacitance 8/ Cxout 25C All 2 5 p

44、F XIN internal load capacitance 8/ Cxin 25C All 2 5 pF Delay time, XIN to H1, x1 and x0.5 modes td(XIN-H1) 25C, -40C to 100C 01 2 8 ns 25C, -55C to 125C 02 8 Input current, feedback enabled, Vil= 0 8/ Iinl 25C, -40C to 100C 01 50 A 25C, -55C to 125C 02 50 Input current, feedback enabled, Vil= Vih8/

45、Iinh 25C, -40C to 100C 01 -50 A 25C, -55C to 125C 02 -50 Timing requirements for EXTCLK, all modesRise time, EXTCLK 8/ tr(EXTCLK) See figure 4 F = Fmax, x0.5 and x1 modes 25C, -40C to 100C 01 1 ns 25C, -55C to 125C 02 1 F Fmax 25C, -40C to 100C 01 4 25C, -55C to 125C 02 4 Fall time, EXTCLK 8/ tf(EXT

46、CLK) F = Fmax, x0.5 and x1 modes 25C, -40C to 100C 01 1 ns 25C, -55C to 125C 02 1 F Fmax 25C, -40C to 100C 01 4 25C, -55C to 125C 02 4 Pulse duration, EXTCLK low 8/ tw(EXTCLKL) x5 mode 25C, -40C to 100C 01 21 ns 25C, -55C to 125C 02 21 x1 mode 25C, -40C to 100C 01 5.5 25C, -55C to 125C 02 5.5 x0.5 m

47、ode 25C, -40C to 100C 01 4 25C, -55C to 125C 02 4 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03610 REV B PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ 3/ 3.0 V DVDD 3.6 V 1.71 V CVDD 1.89 V unless otherwise specified Temperature, TCDevice type Limits Unit Min Max Timing re