JEDEC JESD79-2F-2009 DDR2 SDRAM SPECIFICATION.pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD79-2FNovember 2009JEDECSTANDARDDDR2 SDRAM SPECIFICATION(Revision of JESD79-2E)NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and ap

2、proved by the JEDEC legal Counsel.JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining

3、 with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or proc

4、esses. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications.The information included in JEDEC standards and publications represents a sound approach to product specification and appl

5、ication, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization, there are procedures whereby a JEDEC standard or publication mya be further processed and ultimately become an ANSI standard.No claims to be in conformance with this standard may be made unless al

6、l requirements stated in the standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org.Published byJEDEC Solid State Technology Association 20093103 No

7、rth 10th Street, Suite 240-SArlington, VA 22201This document may be downloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material.Price: Please refer to the current Catalog of JEDEC E

8、ngineering Standards and Publications online athttp:/www.jedec.org/Catalog/catalog.cfmPrinted in the U.S.A.All rights reservedPLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the Electronic Industries Alliance and may not be reproduced without permission. Organizations may obtain permis

9、sion to reproduce a limited number of copies through entering into a license agreem ent. For inform ation, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 This page intentionally left blank.JEDEC Standard No. 79-2FContents

10、1 Scope . 12 Package ballout UDQS corresponds to the data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMR(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS, U

11、DQS, and RDQS to provide differen-tial pair signaling to the system during both reads and writes. A control bit at EMR(1)A10 enables or disables all complementary data strobe signals.In this data sheet, “differential DQS signals“ refers to any of the following with EMR(1)A10 = 0x4 DQS/DQSx8 DQS/DQS

12、if EMR(1)A11 = 0x8 DQS/DQS, RDQS/RDQS, if EMR(1)A11 = 1x16 LDQS/LDQS and UDQS/UDQS “single-ended DQS signals“ refers to any of the following with EMR(1)A10 = 1x4 DQSx8 DQS if EMR(1)A11 = 0x8 DQS, RDQS, if EMR(1)A11 = 1x16 LDQS and UDQSNC No Connect: No internal electrical connection is present.VDDQS

13、upply DQ Power Supply: 1.8 V +/- 0.1 VVSSQSupply DQ Ground2 Package ballout accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. T

14、he address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0-BA2 select the bank; A0-A15 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst acces

15、s and to determine if the auto precharge command is to be issued.Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.3.3 Power-up and initiali

16、zationDDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation.For DDR2 SDRAMs, both bits BA0 and BA1 must be decoded for Mode/Extended Mode Register Set (MRS/EMRS) commands. Users must initialize all f

17、our Mode Registers. The registers may be initialized in any order.SelfIdleSettingEMR(2)BankPrechargingPowerWritingACTRDARDSRFREFCKEL(E)MRSCKEHCKEHCKELWRAutomatic SequenceCommand SequenceRDAWRARDPR, PRAPRRefreshingRefreshingDownPowerDownActivewith RDAReadingwithWRAActivePrechargeReadingWritingPR(A) =

18、 Precharge (All)(E)MRS = (Extended) Mode Register SetSRF = Enter Self RefreshREF = RefreshCKEL = CKE LOW, enter Power DownCKEH = CKE HIGH, exit Power Down, exit Self RefreshACT = ActivateWR(A) = Write (with Autoprecharge)RD(A) = Read (with Autoprecharge)All banks prechargedActivatingCKEHRDWRCKELMR,E

19、MR(1)CKELSequenceInitializationOCDcalibrationCKELCKEL CKELAutoprechargeAutoprecharge PR, PRA PR, PRANOTE Use caution with this diagram. It is intended to provide a floorplan of the possible state transitions and the commands to control them, not all details. In particular situations involving more t

20、han one bank, enabling/disabling on-die termination, Power Down entry/exit, timing restrictions during state transitions, among other things, are not captured in full detail.Figure 13 DDR2 SDRAM simplified state diagramWRWRAEMR(3)JEDEC Standard No. 79-2FPage 173.3.1 Power-up and initialization seque

21、nceThe following sequence is required for Power-up and Initialization.a) Either one of the following sequence is required for Power-up.a1) While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT*1at a LOW state (all other inputs may be undefined.) The VDD voltage ramp time must be no

22、greater than 200 ms from when VDD ramps from 300 mV to VDD min; and during the VDD voltage ramp, |VDD-VDDQ| 0.3 volts. Once the ramping of the supply voltages is complete (when VDDQ crosses VDDQ min), the supply voltage specifications provided in section 6, Table 17 Recommended DC operating conditio

23、ns (SSTL_1.8), prevail.- VDD, VDDL and VDDQ are driven from a single power converter output, AND- VTT is limited to 0.95 V max, AND- Vref tracks VDDQ/2, VREF must be within +/- 300 mV with respect to VDDQ/2 during supply ramp time.- VDDQ VREF must be met at all times.a2) While applying power, attemp

24、t to maintain CKE below 0.2 x VDDQ and ODT*1at a LOW state, all other inputs may be undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch-up. During the ramping of the supply voltages, VDD VDDL VDDQ must be maintained and is applicable to b

25、oth AC and DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the ramping of the supply voltages is complete, the supply voltage specifications provided in section 6, Table 17 Recommended DC operating conditions (SSTL_1.8), prevail.- Apply VDD/V

26、DDL before or at the same time as VDDQ.- VDD/VDDL voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD min- Apply VDDQ before or at the same time as VTT.- The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must be n

27、o greater than 500 ms.(Note: While VDD is ramping, current may be supplied from VDD through the DRAM to VDDQ.)- Vref must track VDDQ/2, Vref must be within +/- 300 mv with respect to VDDQ/2 during supply ramp time.- VDDQ VREF must be met at all times.-Apply VTT.- The VTT voltage ramp time from when

28、VDDQ min is achieved on VDDQ to when VTT min is achieved on VTT must be no greater than 500 ms.b) Start clock and maintain stable condition.c) For the minimum of 200 us after stable power (VDD, VDDL, VDDQ, VREF and VTT are between their minimum and maximum values as stated in section 6, Table 17 Rec

29、ommended DC operating conditions (SSTL_1.8) and stable clock (CK, CK), then apply NOP or Deselect & take CKE HIGH.d) Wait minimum of 400 ns then issue precharge all command. NOP or Deselect applied during 400 ns period.e) Issue an EMRS command to EMR(2). (To issue EMRS command to EMR(2), provide LOW

30、 to BA0 and BA2, HIGH to BA1.)f) Issue an EMRS command to EMR(3). (To issue EMRS command to EMR(3), provide LOW to BA2, HIGH to BA0 and BA1.)g) Issue EMRS to enable DLL. (To issue DLL Enable command, provide LOW to A0, HIGH to BA0 and LOW to BA1-BA2 and A13-A15. And A9=A8=A7=LOW must be used when is

31、suing this command.)h) Issue a Mode Register Set command for DLL reset.(To issue DLL Reset command, provide HIGH to A8 and LOW to BA0-BA2, and A13-A15.)i) Issue a precharge all command.j) Issue 2 or more auto-refresh commands.k) Issue a MRS command with LOW to A8 to initialize device operation. (i.e

32、. to program operating parameters 3 Functional Descripton (contd)3.3 Power-up and initialization (contd)JEDEC Standard No. 79-2FPage 18without resetting the DLL.)l) At least 200 clocks after step h, execute OCD Calibration (Off Chip Driver impedance adjustment).If OCD calibration is not used, EMRS t

33、o EMR(1) to set OCD Calibration Default (A9=A8=A7=HIGH) followed by EMRS to EMR(1) to exit OCD Calibration Mode (A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1).m) The DDR2 SDRAM is now ready for normal operation.*1: To guarantee ODT off, VREF must be valid and a LOW level mus

34、t be applied to the ODT pin.3.4 Programming the mode and extended mode registersFor application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL

35、 disable function, driver impedance, additive CAS latency, ODT (On Die Termination), single-ended strobe, and OCD (off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register (MR) or Ext

36、ended Mode Registers (EMR(#) can be altered by re-executing the MRS or EMRS Commands. Even if the user chooses to modify only a subset of the MR or EMR(#) variables, all variables within the addressed register must be redefined when the MRS or EMRS commands are issued.MRS, EMRS and Reset DLL do not

37、affect array contents, which means re-initialization including those can be executed at any time after power-up without affecting array contents.3.4.1 DDR2 SDRAM mode register (MR)The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS latency, bu

38、rst length, burst sequence, test mode, DLL reset, WR and various vendor specific options to make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be programmed during initialization for proper operation. The mode regi

39、ster is written by asserting LOW on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 - A15. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to

40、complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on functionality. Burst

41、 length is defined by A0 - A2 with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type is defined by A3, CAS latency is defined by A4 - A6. The DDR2 does not support half clock latency mode. A7 is used for test mode. A8 is used fo

42、r DLL reset. A7 must be set to LOW for normal MRS operation. Write recovery time WR is defined by A9 - A11. Refer to the table for specific codes./CKCKCKECommandPREALLPREALLEMRS MRS REF REF MRS EMRSEMRSANYCMDDLLENABLEDLLRESETOCDDefaultOCDCAL. MODEEXITFollow OCDFlowchart400nstRFCtRFCtRPtRPtMRD tMRD t

43、MRDtOITmin 200 CycleNOPODTtCLtCHtIStISFigure 14 Initialization sequence after power-up3.3 Power-up and initialization (contd)3.3.1 Power-up and initialization sequence (contd)JEDEC Standard No. 79-2FPage 193.4.2 DDR2 SDRAM extended mode registers (EMR(#)3.4.2.1 EMR(1)The extended mode register(1) st

44、ores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, DQS disable, OCD program, RDQS enable. The default value of the extended mode register(1) is not defined, therefore the extended mode register(1) must be programmed during initialization for proper operat

45、ion. The extended mode register(1) is written by asserting LOW on CS, RAS, CAS, WE, HIGH on BA0 and LOW on BA1, while controlling the states of address pins A0 - A15. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register(1). The mode re

46、gister set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register(1). Extended mode register(1) contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 i

47、s used for DLL enable or disable. A1 is used for enabling a reduced strength output driver. A3 - A5 determines the additive latency, A7 - A9 are used for OCD control, A10 is used for DQS disable and A11 is used for RDQS enable. A2 and A6 are used for ODT setting.Address FieldA7 mode0Normal1TestA3 Bu

48、rst Type0 Sequential1 InterleaveA8 DLL Reset0No1YesMode RegisterBA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A00TM CAS Latency BTDLL 0*1WRWrite recovery for autoprechargeA11 A10 A9 WR(cycles)0 0 0 Reserved001 2010 3011 4100 5101 61 1 0 Reserved1 1 1 ReservedA15 A130 Burst LengthBurst LengthA2 A1 A0 BL

49、01040118BA20*1BA1 BA0 MRS mode00 MR01 EMR(1)10 EMR(2)11 EMR(3)DDR2-400DDR2-533DDR2-667DDR2-800*2A12PDA12Active power down exit time0 Fast exit (use tXARD)1 Slow exit (use tXARDS)A6 A5 A4 CAS Latency0 0 0 Reserved0 0 1 Reserved0 1 0 2(Optional)0113(speed bin determined)*3100 41015(speed bin determined)*31106(speed bin determined)*31 1 1 ReservedFigure 15 DDR2 SDRAM mode register set (MRS)NOTE 1 BA2 and A13-A15 are reserved for future use and must be set to 0 when programming the MR.NOTE 2 For DDR2-400/533, WR (write recovery for autoprecharge) min is d