DLA DSCC-VID-V62 12612 REV A-2013 MICROCIRCUIT LINEAR DIFFERENTIAL AMPLIFER LOW POWER MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Under paragraph 6.3, delete title “Package designator” and replace with “Transportation and quantity”. Also, replace the word “rails” with “tube” and delete the words “Tape and”. Sheet 8, Table I, for +VS= 3.3 V condition, rename Input bias current test (II
2、O) to Input offset current test (IIO). - ro 13-08-21 C. SAFFLE Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV A A A PAGE 18 19 20 REV STATUS OF PAGES REV A A A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER DLA L
3、AND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, LINEAR, DIFFERENTIAL AMPLIFER, LOW POWER, MONOLITHIC SILICON 12-06-26 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/
4、12612 REV A PAGE 1 OF 20 AMSC N/A 5962-V072-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12612 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requ
5、irements of a high performance low power differential amplifier microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative contro
6、l number for identifying the item on the engineering documentation: V62/12612 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 THS4524-EP Low power differential amplifier 1.2.2 Case outline(
7、s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 38 MO-153 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot so
8、lder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12612 REV A PAGE 3 1.3 Absolute maximum rat
9、ings. 1/ Supply voltage ( -VSto +VS) . 5.5 V Input/output voltage ( VIN, VOUT, VOCMpins ) -VS 0.7 V to +VS+ 0.7 V Differential input voltage (VID) 1 V Output current (IO) . 100 mA Input current (II) ( VIN, VOCMpins ) . 10 mA Continuous power dissipation (PD) See table under 1.5 Maximum junction temp
10、erature range (TJ) . +150C Maximum junction temperature range (TJ) : Continuous operation, long term reliability . +125C Storage temperature range (TSTG) -65C to +150C Electrostatic discharge (ESD) ratings: Human body model (HBM) . 1300 V Charge device model (CDM) 1000 V Machine model (MM) . 50 V 1.
11、4 Recommended operating conditions. 2/ Supply voltage range (VS) 3.3 V and 5.0 V Operating free-air temperature range (TA) . -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation
12、 of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Use of this product beyond the manufacturers design rules or stated par
13、ameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE
14、 IDENT NO. 16236 DWG NO. V62/12612 REV A PAGE 4 1.5 Thermal characteristics. Thermal metric Symbol Case X Unit Thermal resistance, junction-to-ambient 3/ JA106.9 C/W Thermal resistance, junction-to-case (top) 4/ JC(TOP)59.8 C/W Thermal resistance, junction-to-board 5/ JB66.5 C/W Characterization par
15、ameter, junction-to-top 6/ JT17.1 C/W Characterization parameter, junction-to-board 7/ JB66.1 C/W _ 3/ The thermal resistance, junction-to-ambient under natural convection is obtained in a simulation on a JEDEC standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2
16、a. 4/ The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 5/ The thermal resistance, junction-to-board is obtained by simulating i
17、n an environment with a ring cold plate fixture to control the printed circuit board (PCB) temperature, as described in JESD51-8. 6/ Characterization parameter, junction-to-top (JT) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtainin
18、g JA, using a procedure described in JESD51-2a (sections 6 and 7). 7/ Characterization parameter, junction-to-board (JB) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 an
19、d 7). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12612 REV A PAGE 5 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 - Registered and Stand
20、ard Outlines for Semiconductor Devices EIA/JESD51-2a - Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) EIA/JEDEC 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages EIA/JESD51-8 - Integrated Circuits Thermal Test Metho
21、d Environment Conditions Junction-to-Board (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) AMERICAN NATIONAL STANDARDS INSTITUTE ANSI SEMI STANDARD G30-88 - Test Method for Junction-
22、to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) 3. REQUIRE
23、MENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the m
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