JEDEC JESD79-3-1A 01-2013 Addendum No 1 to JESD79 3 1 35 V DDR3L 800 DDR3L 1066 DDR3L 1333 DDR3L 1600 and DDR3L 1866 (Minor Editorial Revision of JESD79 3 1A January 2013).pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD7931A.01MAY 2013JEDECSTANDARDAddendum No. 1 to JESD793 1.35 V DDR3L800, DDR3L1066,DDR3L1333, DDR3L1600, and(Minor Editorial Revision of JESD7931A, January 2013)DDR3L1866 NOTICEJEDEC standards and publications contain material that has been prepared, review

2、ed, andapproved through the JEDEC Board of Directors level and subsequently reviewed and approvedby the JEDEC legal counsel.JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeab

3、ility andimprovement of products, and assisting the purchaser in selecting and obtaining with minimumdelay the proper product for use by those other than JEDEC members, whether the standard is tobe used either domestically or internationally.JEDEC standards and publications are adopted without regar

4、d to whether or not their adoptionmay involve patents or articles, materials, or processes. By such action JEDEC does not assumeany liability to any patent owner, nor does it assume any obligation whatever to parties adoptingthe JEDEC standards or publications.The information included in JEDEC stand

5、ards and publications represents a sound approach toproduct specification and application, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard orpublication may be further processed and ultimately become an ANSI s

6、tandard.No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard orpublication should be addressed to JEDEC at the address below, or call (703) 9077559 orww

7、w.jedec.orgPublished byJEDEC Solid State Technology Association 20133103 North 10th StreetSuite 240 SouthArlington, VA 222012107This document may be downloaded free of charge; however JEDEC retains thecopyright on this material. By downloading this file the individual agrees not tocharge for or rese

8、ll the resulting material.PRICE: Please refer to www.jedec.orgPrinted in the U.S.A.All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by the JEDEC Solid State Technology Associationand may not be reproduced without permission.Organizations may obtain permission to reproduce a

9、limited number of copies through entering into a license agreement. For information, contact:JEDEC Solid State Technology Association3103 North 10th Street, Suite 240SArlington, Virginia 22201or call (703) 9077559JEDEC Standard No. 79-3-1A.01Page 11.35 V DDR3-800, DDR3L-1066, DDR3L-1333, DDR3L-1600,

10、 and DDR3L-1866(From JEDEC Board Ballot, JCB-10-12 and JCB-11-95, formulated under the cognizance of the JC-42.3 Subcommittee on Volatile RAM.)1 ScopeThe JESD79-3 document defines DDR3L SDRAM, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments with

11、the exception of what is stated within this standard. The purpose of this standard is to define the DDR3L specifications that supersede the DDR3 specifications as defined in JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600, and DDR3-1866 titles in JESD79-3 are to be interpreted as DDR3

12、L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600,and DDR3L-1866, respectively, when applying towards DDR3L definition; unless specifically stated otherwise.2 DDR3L VDD/VDDQ requirementsNOTE 1 Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ(t) over a very long

13、 period of time (e.g., 1 sec).NOTE 2 If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.NOTE 3 Under these supply voltages, the device operates to this DDR3L specifcation.NOTE 4 Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in

14、 reset while VDD and VDDQ are changed for DDR3 operation (see Figure 1).Table 1 Input/output functional descriptionSymbol Type FunctionVDDSupply Power Supply: DDR3L operation = 1.283 V to 1.45 V; DDR3 operation = 1.425 V to 1.575 VVDDQSupply DQ Power Supply: DDR3L operation = 1.283 V to 1.45 V; DDR3

15、 operation = 1.425 V to 1.575 VTable 2 Recommended DC Operating Conditions - DDR3L (1.35 V) operationSymbol Parameter/Condition min Typ max Units NotesVDDSupply voltage 1.283 1.35 1.45 V 1,2,3,4VDDQSupply voltage for Output 1.283 1.35 1.45 V 1,2,3,4JEDEC Standard No. 79-3-1A.01Page 22 DDR3L VDD/VDDQ

16、 requirements (contd)NOTE 1 If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.NOTE 2 Under 1.5 V operation, this DDR3L device operates to the DDR3 specifcations under the same speed timings as defined for this device.NOTE 3 Once initialized for DDR3 operation, DDR3

17、L operation may only be used if the device is in reset while VDDand VDDQare changed for DDR3L operation (see Figure 1).Figure 1 VDDQ/VDDQVoltage Switch Between DDR3L and DDR3Table 3 Recommended DC Operating Conditions - DDR3 (1.5 V) operationSymbol Parameter/Condition min Typ max Units NotesVDDSuppl

18、y voltage 1.425 1.5 1.575 V 1,2,3VDDQSupply voltage for Output 1.425 1.5 1.575 V 1,2,3JEDEC Standard No. 79-3-1A.01Page 33 1.35 V DDR3L AC and DC Logic Input Levels for Single-Ended Signals3.1 AC and DC Input Levels for Single-Ended Command and Address Signals3.2 AC and DC Input Levels for Single-En

19、ded Data SignalsTable 4 Single-Ended AC and DC Input Levels for Command and AddressSymbol ParameterDDR3L-800, DDR3L-1066 DDR3L-1333, DDR3L-1600 DDR3L-1866Unit Notesmin max min max min maxVIH.CA(DC90) DC input logic high Vref + 0.09 VDDVref + 0.09 VDDVref + 0.09 VDDV1VIL.CA(DC90) DC input logic low V

20、SSVref - 0.09 VSSVref - 0.09 VSSVref - 0.09 V 1VIH.CA(AC160) AC input logic high Vref + 0.160 Note 2 Vref + 0.160 Note 2 - - V 1, 2, 5VIL.CA(AC160) AC input logic low Note 2 Vref - 0.160 Note 2 Vref - 0.160 - - V 1, 2, 5VIH.CA(AC135) AC input logic high Vref + 0.135 Note 2 Vref + 0.135 Note 2 Vref +

21、 0.135 Note 2 V 1, 2, 5VIL.CA(AC135) AC input logic low Note 2 Vref - 0.135 Note 2 Vref - 0.135 Note 2 Vref - 0.135 V 1, 2, 5VIH.CA(AC125) AC input logic high - - - - Vref + 0.125 Note 2 V 1, 2, 5VIL.CA(AC125) AC input logic low - - - - Note 2 Vref - 0.125 V 1, 2, 5VRefCA(DC) Reference Voltage for A

22、DD, CMD inputs0.49 * VDD0.51 * VDD0.49 * VDD0.51 * VDD0.49 * VDD0.51 * VDDV3, 4NOTE 1 For input only pins except RESET#. Vref = VrefCA(DC).NOTE 2 See JESD79-3E, 9.6 “Overshoot and Undershoot Specifications”, 9.6.1.NOTE 3 The AC peak noise on VRefmay not allow VRefto deviate from VRefDQ(DC)by more th

23、an +/-1% VDD(for reference: approx. +/- 13.5 mV). NOTE 4 For reference: approx. VDD/2 +/- 13.5 mV NOTE 5 These levels apply for 1.35 Volt (see Table 4) operation only. If the device is operated at 1.5 V (see Table 23), the respective levels in JESD79-3 (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC1

24、50), VIH/L.CA(AC135), VIH/L.CA(AC125), etc.) apply. The 1.5 V levels (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125), etc.) do not apply when the device is operated in the 1.35 voltage range.Table 5 Single-Ended AC and DC Input Levels for DQ and DMSymbol Paramete

25、rDDR3L-800, DDR3L-1066 DDR3L-1333, DDR3L-1600 DDR3L-1866Unit Notesmin max min max min maxVIH.DQ(DC90) DC input logic high Vref + 0.09 VDDVref + 0.09 VDDVref + 0.09 VDDV1VIL.DQ(DC90) DC input logic low VSSVref - 0.09 VSSVref - 0.09 VSSVref - 0.09 V 1VIH.DQ(AC160) AC input logic high Vref + 0.160 Note

26、 2 - - - - V 1, 2, 5VIL.DQ(AC160) AC input logic low Note 2 Vref - 0.160 - - - - V 1, 2, 5VIH.DQ(AC135) AC input logic high Vref + 0.135 Note 2 Vref + 0.135 Note 2 - - V 1, 2, 5VIL.DQ(AC135) AC input logic low Note 2 Vref - 0.135 Note 2 Vref - 0.135 - - V 1, 2, 5VIH.DQ(AC130) AC input logic high - -

27、 - - Vref + 0.130 Note 2 V 1, 2, 5VIL.DQ(AC130) AC input logic low - - - - Note 2 Vref - 0.130 V 1, 2, 5VRefDQ(DC) Reference Voltage for DQ, DM inputs0.49 * VDD0.51 * VDD0.49 * VDD0.51 * VDD0.49 * VDD0.51 * VDDV3, 4NOTE 1 For input only pins except RESET#. Vref = VrefDQ(DC).NOTE 2 See JESD79-3E, 9.6

28、 “Overshoot and Undershoot Specifications”, 9.6.2.NOTE 3 The AC peak noise on VRefmay not allow VRefto deviate from VRefDQ(DC)by more than +/-1% VDD(for reference: approx. +/- 13.5 mV).NOTE 4 For reference: approx. VDD/2 +/- 13.5 mV.NOTE 5 These levels apply for 1.35 Volt (see Table 5) operation onl

29、y. If the device is operated at 1.5 V (see Table 24), the respective levels in JESD79-3 (VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135), etc. ) apply. The 1.5 V levels (VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135), etc. ) do not apply when the device is oper

30、ated in the 1.35 voltage range.JEDEC Standard No. 79-3-1A.01Page 44 1.35 V DDR3L Electrical Characteristics and AC TimingNOTE 1 (AC/DC referenced for 1 V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate)NOTE 2 The tIS(base) AC135 specifications are adjusted from the tIS(base) AC

31、160 specification by adding an additional 125 ps for DDR3L-800/1066 or 100 ps for DDR3L-1333/1600 of derating to accommodate for the lower alternate threshold of 135 mV and another 25 ps to account for the earlier reference point (160 mV - 135 mV) / 1 V/ns.NOTE 3 The tIS(base) AC125 specifications a

32、re adjusted from the tIS(base) AC135 specification by adding an additional 75 ps for DDR3L-1866 of derating to accommodate for the lower alternate threshold of 135 mV and another 10 ps to account for the earlier reference point (135 mV - 125 mV) / 1 V/ns.Table 6 Timing Parameters by Speed BinaParame

33、ter SymbolDDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866Units Notesmin max min max min max min max min maxData TimingData setup time to DQS, DQS# referenced to Vih.DQ(ac) / Vil.DQ(ac) levelstDS(base) AC160SR = 1V/ns90-40-psRefer toJESD79-3d, 17tDS(base) AC135SR = 1V/ns140 - 90 - 45 - 25 - - -

34、 psRefer toJESD79-3d, 17tDS(base) AC130SR = 2V/ns-70 - psRefer toJESD79-3dData hold time from DQS, DQS# referenced to Vih.DQ(dc) / Vil.DQ(dc) levelstDH(base) DC90SR = 1V/ns160 - 110 - 75 - 55 - - - psRefer toJESD79-3d, 17tDH(base) DC90SR = 2V/ns-75-psRefer toJESD79-3dCommand and Address TimingComman

35、d and Address setup time to CK, CK# referenced to Vih.CA(ac) / Vil.CA(ac) levelstIS(base) AC160SR = 1V/ns215 - 140 - 80 - 60 - - - psRefer toJESD79-3b, 16tIS(base) AC135SR = 1V/ns365 - 290 - 205 - 185 - 65 - psRefer toJESD79-3b, 16tIS(base) AC125SR = 1V/ns-150-psRefer toJESD79-3b, 16Command and Addr

36、ess hold time from CK, CK# referenced to Vih.CA(dc) / Vil.CA(dc) levelstIH(base) DC90SR = 1V/ns285 - 210 - 150 - 130 - 110 - psRefer toJESD79-3b, 16aThe setup and hold parameters in this table apply for 1.35 V (see Table 2) operation only. If the device is operated at 1.5 V (see Table 3), the respec

37、tive parameters in JESD79-3 ( tIS(base, AC175), tIS(base, AC150), tIH(base, DC100), tDS(base, AC175), tDS(base, AC150), tDH(base, DC100), etc.) apply. The 1.5 V setup/hold parameters ( tIS(base, AC175), tIS(base, AC150), tIH(base, DC100), tDS(base, AC175), tDS(base, AC150), tDH(base, DC100), etc.) d

38、o not apply when the device is operated in the 1.35 voltage range.NOTE 1 The general notes from JESD79-3E, 13.4, apply to Table 6.NOTE 2 VDD=VDDQ = 1.35 V +0.100/- 0.067VTable 7 ADD/CMD Setup and Hold Base-Values for 1 V/nsSymbol Reference DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866 Units

39、NotetIS(base) AC160 VIH/L(AC): SR=1 V/ns 215 140 80 60 - ps 1tIS(base) AC135 VIH/L(AC): SR=1 V/ns 365 290 205 185 65 ps 1, 2tIS(base) AC125 VIH/L(AC): SR=1 V/ns - - - - 150 ps 1, 3tIH(base) DC90 VIH/L(DC): SR=1 V/ns 285 210 150 130 110 ps 1JEDEC Standard No. 79-3-1A.01Page 54.1 Address / Command Set

40、up, Hold and DeratingTable 8 Derating values DDR3L-800/1066/1333/1600 tIS/tIH - AC/DC basedtIS, tIH derating in ps AC/DC basedAC160 Threshold - VIH(ACAC)=VREF(DC)+160 mV, VIL(AC)=VREF(DC)-160 mVCK,CK# Differential Slew Rate4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/nstIS tI

41、H tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIHCMD/ADDSlewrateV/ns2.0 80 45 80 45 80 45 88 53 96 61 104 69 112 79 120 951.5 53 30 53 30 53 30 61 38 69 46 77 54 85 64 93 801.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 500.9 -1 -3 -1 -3 -1 -3 7 5 15 13 23 21 31 31 39 470.8 -3 -8 -3 -8 -3 -8 5 1 1

42、3 9 21 17 29 27 37 430.7 -5 -13 -5 -13 -5 -13 3 -5 11 3 19 11 27 21 35 370.6 -8 -20 -8 -20 -8 -20 0 -12 8 -4 16 4 24 14 32 300.5 -20 -30 -20 -30 -20 -30 -12 -22 -4 -14 4 -6 12 4 20 200.4 -40 -45 -40 -45 -40 -45 -32 -37 -24 -29 -16 -21 -8 -11 0 5Table 9 Derating values DDR3L-800/1066/1333/1600 tIS/tI

43、H - AC/DC based Alternate AC135 ThresholdtIS, tIH derating in ps AC/DC basedAlternate AC135 Threshold - VIH(AC)=VREF(DC)+135 mV, VIL(AC)=VREF(DC)-135 mVCK,CK# Differential Slew Rate4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/nstIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH

44、tIS tIH tIS tIHCMD/ADDSlewrateV/ns2.0 68 45 68 45 68 45 76 53 84 61 92 69 100 79 108 951.5 45 30 45 30 45 30 53 38 61 46 69 54 77 64 85 801.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 500.9 2 -3 2 -3 2 -3 10 5 18132621343142470.8 3 -8 3 -8 3 -8 11 1 19 9 27 17 35 27 43 430.7 6 -13 6 -13 6 -13 14 -5 22 3

45、30 11 38 21 46 370.6 9 -20 9 -20 9 -20 17 -12 25 -4 33 4 41 14 49 300.5 5 -30 5 -30 5 -30 13 -22 21 -14 29 -6 37 4 45 200.4 -3 -45 -3 -45 -3 -45 6 -37 14 -29 22 -21 30 -11 38 5JEDEC Standard No. 79-3-1A.01Page 64.1 Address / Command Setup, Hold and Derating (contd)Table 10 Derating values DDR3L-1866

46、 tIS/tIH - AC/DC based Alternate AC125 ThresholdTable 11 Required time tVACabove VIH(AC) below VIL(AC) for valid ADD/CMD transitionNOTE Rising input signal shall become equal to or greater than VIH(ac) level and falling input signal shall become equal to or less than VIL(ac) level.tIS, tIH derating

47、in ps AC/DC basedAlternate AC125 Threshold - VIH(AC)=VREF(DC)+125 mV, VIL(AC)=VREF(DC)-125 mVCK,CK# Differential Slew Rate4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/nstIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIHCMD/ADDSlewrateV/ns2.0 63 45 63 45 63 45 71

48、53 79 61 87 69 95 79 103 951.5 42 30 42 30 42 30 50 38 58 46 66 54 74 64 82 801.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 500.9 3 -3 3 -3 3 -3 11 5 19 13 27 21 35 31 43 470.8 6 -8 6 -8 6 -8 14 1 22 9 30 17 38 27 46 430.7 10 -13 10 -13 10 -13 18 -5 26 3 34 11 42 21 50 370.6 16 -20 16 -20 16 -20 24 -12 3

49、2 4 40 -4 48 14 56 300.5 15 -30 15 -30 15 -30 23 -22 31 -14 39 -6 47 4 55 200.4 13 -45 13 -45 13 -45 21 -37 29 -29 37 -21 45 -11 53 5DDR3L-800/1066/1333/1600 DDR3L-1866Slew Rate V/ns tVAC 160 mV ps tVAC 135 mV ps tVAC 135 mV ps tVAC 125 mV psmin max min max min max min max 2.0 200 - 213 - 200 - 205 -2.0 200 - 213 - 200 - 205 -1.5 173 - 190 - 178 - 184 -1.0 120 - 145 - 133 - 143 -0.9 102 - 130 - 118 - 129 -0.8 80 - 111 - 99 -