JEDEC JESD78E-2016 IC Latch-Up Test.pdf

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1、 JEDEC STANDARD IC Latch-Up Test JESD78E (Revision of JESD78D, November 2011) APRIL 2016 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently review

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7、. Published by JEDEC Solid State Technology Association 2016 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resel

8、l the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 2

9、40 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 78E I0i -i- IC LATCH-UP TEST Contents 1 Scope . 1 1.1 Classification . 1 1.2 Latch-up immunity characterization 2 2 Terms and definitions 2 3 Apparatus and material . 5 3.1

10、 Latch-up tester 5 3.2 Automated test equipment (ATE) 5 3.3 Heat source. 5 4 Procedure 6 4.1 General latch-up test procedure 6 4.2 Detailed latch-up test procedure . 8 4.2.1 I-test . 8 4.2.1.1 Supply current limits . 12 4.2.2 Vsupply overvoltage test 13 4.2.3 Testing dynamic devices 15 4.2.4 DUT dis

11、position . 15 4.2.5 Record keeping 16 5 Latch-up detection criteria 16 6 Summary . 17 Tables 1 Latch-up Immunity Levels . 2 2 Test Matrix . 7 3 Timing specifications for I-test . 10 4 Timing specifications for Vsupply overvoltage test 14 Figures 1 Typical Latch-up test flow 6 2 Test waveform for pos

12、itive I-test . 9 3 Test waveform for negative I-test 9 4 The equivalent circuit for positive input/output I-test latch-up testing . 10 5 The equivalent circuit for negative input/output I-test latch-up testing 11 6 Test waveform for Vsupply overvoltage test . 14 7 The equivalent circuit for Vsupply

13、overvoltage test latch-up testing . 15 Annex A (informative) Examples of special pins that are connected to passive components 18 Annex B (informative) Calculation of Operating Ambient or Operating Case Temperature for a Given Operating Junction Temperature 20 Annex C (informative) Examples of recor

14、ding and reporting data 21 Annex D (informative) Differences between revisions . 23 JEDEC Standard No. 78E -ii- JEDEC Standard No. 78E Page 1 IC LATCH-UP TEST (From JEDEC Board Ballots JCB-16-08, formulated under the cognizance of JC-14.1 Subcommittee on Reliability Test Methods for Packaged Devices

15、.) 1 Scope This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and to define latch-up detection criteria. Latch-up characteristics are extremely important in

16、 determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies. NOTE As these technologies have evolved, it has been nece

17、ssary to adjust this document to the realities of characterization with limits not imagined when the first latch-up document was generated some 25 years ago. Though it would be simpler to make the original limits of 1.5 times the maximum pin operating voltage an absolute level of goodness, the possi

18、bilities of success at this level are limited by the very low voltage technologies, and the medium and high voltage CMOS, BiCMOS and Bipolar technologies (12 V). The concept of maximum stress voltage (MSV) allows the supplier to characterize latch-up in a way that differentiates between latch-up and

19、 EOS. This revision will make it more transparent to the end user that given the limits of certain technologies the subsequent latch-up characterizations are valid. 1.1 Classification There are two classes for latch-up testing. Class I is for testing at room temperature ambient. Class II is for test

20、ing at the maximum operating ambient temperature (Ta) or maximum operating case temperature (Tc) or maximum operating junction temperature (Tj) in the data sheet. For Class II testing at the maximum operating Ta or Tc, the ambient temperature or case temperature (Tc) shall be established at the requ

21、ired test value. For Class II testing at the maximum operating Tj, the ambient temperature Ta or the case temperature Tc should be selected to achieve a temperature characteristic of the junction temperature for a given device operating mode(s) during latch-up testing. The maximum operating ambient

22、or case temperature during stress may be calculated based on the methods detailed in Annex B. The values used in Class II testing shall be recorded in the final report. NOTE Elevated temperature will reduce latch-up resistance, and class II testing is recommended for devices that are required to ope

23、rate at elevated temperature. JEDEC Standard No. 78E Page 2 1.2 Latch-up immunity characterization Product latch-up immunity is characterized by an I/O current injection value and Vsupply overvoltage value that does not result in a latch-up as defined in this test method. Refer to Table 1 for the re

24、commended range of current and voltage stress, and Table 2 footnotes b, c, and d for the clamping conditions. The actual achieved force current or voltage levels may be reported as mentioned in Annex C. Table 1 Latch-up immunity levels Immunity Level Test Magnitude of Trigger Force Current or Voltag

25、e A Positive I-Test 100 mAa Negative I-Test 100 mAa Overvoltage Test 1.5 x VDD or MSV, whichever is lessb B If immunity level A cannot be achieved a The actual injected current may be less than 100mA if pin voltage clamping limits are reached (See Table 2). If Latch-up does not occur in such a condi

26、tion, then this constitutes a passing test with Immunity Level A. Otherwise, it is classified with Immunity Level B. b The actual applied voltage may be less than 1.5 x VDD or MSV if Vsupply current clamping limits are reached (See Table 2). If Latch-up does not occur in such a condition, then this

27、constitutes a passing test with Immunity Level A. Otherwise, it is classified with Immunity Level B. 2 Terms and definitions The following terms and definitions apply to this test method. cool-down time: The period of time between successive applications of trigger pulses, or the period of time betw

28、een the removal of the Vsupply voltage and the application of the next trigger pulse. (See Figure 2, Figure 3, Figure 6, and Table 3.) DUT: The device under test. dynamic devices: Devices requiring clocking in order to guarantee a stable state while being tested. GND (Ground): The common or zero-pot

29、ential pin(s) of the DUT. NOTE 1 Ground pins are not latch-up tested. NOTE 2 A ground pin is sometimes called Vss. input pins: All address, data-in control, Vref, and similar pins. I/O (bidirectional) pins: Device pins that can be made to operate as an input or an output or in a high-impedance state

30、. JEDEC Standard No. 78E Page 3 2 Terms and definitions (contd) Isupply: The total supply current in each Vsupply pin (or pin group) with the DUT biased as indicated in Table 2. I-test: A latch-up test that supplies positive and negative current pulses to the pin under test. latch-up: A state in whi

31、ch a low-impedance path, resulting from an overstress that triggers a parasitic thyristor structure, persists after removal or cessation of the triggering condition. NOTE 1 The overstress can be a voltage or current surge, an excessive rate of change of current or voltage, or any other abnormal cond

32、ition that causes the parasitic thyristor structure to become regenerative. NOTE 2 Latch-up will not damage the device provided that the current through the low-impedance path is sufficiently limited in magnitude or duration. logic-high: A level within the more positive (less negative) of the two ra

33、nges of logic levels chosen to represent the logic states. NOTE 1 For digital devices, the maximum value of the high logic level voltage is used for latch-up testing. The maximum logic high level is designated as Vmax. NOTE 2 For non-digital devices, the maximum operating voltage that can be applied

34、 to that pin as defined in the device specification is used for latch-up testing. logic-low: A level within the more negative (less positive) of the two ranges of logic levels chosen to represent the logic states. NOTE 1 For digital devices, the minimum value of the low logic level voltage is used f

35、or latch-up testing. The minimum logic low level is designated as Vmin. NOTE 2 For non-digital devices, the minimum operating voltage that can be applied to that pin as defined in the device specification is used for latch-up testing. maximum Vsupply; maximum operating voltage: The maximum supply vo

36、ltage at which a device is specified to operate in compliance with the applicable device specification. NOTE 1 “Maximum” refers to the magnitude of supply voltage and can be either positive or negative. NOTE 2 The maximum voltage is not the absolute maximum rated voltage, i.e., the voltage beyond wh

37、ich permanent damage is likely. JEDEC Standard No. 78E Page 4 2 Terms and definitions (contd) maximum stress voltage (MSV): The maximum voltage allowed to be placed on any given pin during latch-up immunity testing without causing irreversible damage to the device from a catastrophic breakdown of th

38、e silicon device or circuit not related to latch-up. NOTE 1 A positive MSV is higher than the maximum operating voltage and a negative MSV is lower than the minimum operating voltage. NOTE 2 MSV is NOT the same as the absolute maximum voltage rating (AMR) from the device data sheet. MSV applies to l

39、atch-up testing only, protecting the DUT from physical damage from stress mechanisms not directly related to latch-up. An example of an unrelated stress is one exceeding the destructive breakdown voltage of a pin resulting in non-latch-up induced catastrophic breakdown of the silicon device / circui

40、t. MSV may be different for each pin and each polarity during testing, depending on process technology and circuit topology. In many medium and high voltage designs (12 V), MSV may be nearly the same value as AMR. Further, the MSV value depends on the pulse width used during latch-up testing. Shorte

41、r pulse widths may allow a higher value for MSV. Therefore, the MSV value chosen should take into account the pulse width as well as process technology and circuit topology. “no connect” pin: A pin that has no internal connection and that can be used as a support for external wiring without disturbi

42、ng the function of the device. NOTE All “no connect” pins shall be left in an open (floating) state during latch-up testing. nominal Isupply (Inom): The measured dc supply current for each Vsupply pin (or pin group) with the DUT biased at the test temperature as defined in clause 4 and Table 2. outp

43、ut pin: A device pin that generates a signal or voltage level as a normal function during the normal operation of the device. NOTE Output pins, though left in an open (floating) state during testing of other pin types, are latch-up tested. power supply: A component in the test system that supplies v

44、oltage and current to the DUT. preconditioned pin: A device pin that has been placed in a defined state or condition (input, output, high impedance, etc.) by applying control vectors to the DUT. test condition: The test temperature, supply voltage, current limits, voltage limits, clock frequency, in

45、put bias voltages, and preconditioning vectors applied to the DUT during the latch-up test. timing-related input pin: A pin such as clock crystal oscillator, charge pump circuit, etc., required to place the DUT in a normal operating mode. NOTE Required timing signals may be applied by the latch-up t

46、ester, external equipment, and/or external components as appropriate. trigger pulse: The positive or negative current pulse (I-Test) or voltage pulse (Vsupply overvoltage test) applied to any pin under test in an attempt to induce latch-up (see Figure 2, Figure 3 and Figure 6). JEDEC Standard No. 78

47、E Page 5 2 Terms and definitions (contd) trigger duration: The duration of an applied pulse from the trigger source. (See Figure 2, Figure 3, Figure 6 and Table 3.) Vsupply pin (or pin group): A supply pin is any pin that provides current to a circuit. Supply pins typically transmit no information (

48、such as digital or analog signals, timing, clock signals, voltage or current reference levels). For the purpose of latch-up testing, power pins are treated as supply pins. NOTE 1 Generally, it is permissible to treat equal-potential voltage source pins as one Vsupply pin (or pin group) and connect t

49、hem to one power supply. NOTE 2 When forming Vsupply pins (or pin groups), the combination of Vsupply pins with significantly different supply current levels is not recommended as this would make it difficult to detect significant current changes on low supply current pins. Vsupply overvoltage test: A latch-up test that supplies overvoltage pulses to the Vsupply pin (or pin group) under test. 3 Apparatus and material The apparatus required for this test method includes the following: 3.1 Latch-up tester Test equipment capable of performing the tests as specified in this docum