JEDEC JEP157-2009 Recommended ESD-CDM Target Levels.pdf

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1、JEDEC PUBLICATION Recommended ESD-CDM Target Levels JEP157 OCTOBER 2009 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved b

2、y the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with m

3、inimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes.

4、 By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and applicati

5、on, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all req

6、uirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2009 3103 Nort

7、h 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Please refer to the current Catalog o

8、f JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduc

9、e a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or call (703) 907-7559 JEDEC Publication No. 157 -i- RECOMMENDED ESD-CDM TARGET LEVELS Foreword C

10、DM has become the primary real world ESD event metric describing ESD charging and rapid discharge events in automated handling, manufacturing and assembly of IC devices. Its importance has dramatically increased in the last few years as package feature sizes, capacitance and pin count have scaled up

11、ward. In recent years, arbitrary CDM protection levels have been specified as IC qualification goals with little background information available on actual/realistic CDM event levels and the protection methods available in controls and device design for safe production of IC components. The rapid ad

12、vancement of IC technology scaling, coupled with the increased demand for high speed circuit performance, are making it increasingly difficult to guarantee the commonly customer specified “500V” CDM specification. At the same time, the required static control methods available for production area CD

13、M protection at each process step have not been fully outlined. Therefore, a realistic CDM specification target must be defined in terms of available and commonly practiced CDM control methods, and also must reflect current ESD design constraints. By balancing improved static control technology spec

14、ific to CDM, and limited ESD design capability in todays leading technologies, we recommend a CDM specification target level of 250V. This is considered to be a realistic and safe CDM level for manufacturing and handling of todays products using basic CDM control methods. At the same time we show th

15、at the current trend of silicon technology scaling will continue to place further restrictions on achievable CDM levels. It is therefore necessary that we present a realistic CDM roadmap for consideration by the industry moving forward to the next two levels of scaled technologies approaching 22nm a

16、nd beyond. Introduction This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD CDM level requirements. We will show through this document why a more realistic definition o

17、f the ESD CDM target levels for components is not only essential but is also urgent. The document is organized in different clauses with additional information in the annexes to give as many technical details as possible to support the purpose given in the abstract. Frequently Asked Questions (FAQ)

18、are also included in Annex F so that the reader can readily find critical information without having to scan through the whole document. Additionally, these FAQs are intended to avoid any misconceptions that commonly occur while interpreting the data and the conclusions herein. All component level E

19、SD testing specified within this document adheres to the methods defined in the appropriate JEDEC and ANSI/ESDA as well as JEITA specifications. JEDEC Publication No. 157 -ii- RECOMMENDED ESD-CDM TARGET LEVELS Contents 1 Scope.1 2 References.1 3 Terms and Definitions.5 4 CDM Background and History .

20、7 5 CDM Challenges to IC Component ESD Design .10 5.1 Introduction.10 5.2 The CDM Event from the ESD Designers Perspective .10 5.3 Design Techniques for CDM11 5.4 Technology Scaling Effects on CDM ESD Robustness14 5.5 Examples of CDM Impact on Integrated Circuit ESD Design .16 5.6 Package Effects an

21、d Package Trends21 5.7 ESD Designers Perspective on Realistic CDM Targets 24 5.8 Further Technology Scaling Effects and Additional Impact to Realistic CDM Targets.26 6 CDM Related ESD Control in Assembly Lines.27 6.1 Basic Idea of CDM Protection28 6.2 Process Related Risk Analysis29 6.3 Process Capa

22、bility R. Gauthier, K. Chatty, S. Mitra, H. Li;, “Capacitance investigation of diodes and SCRs for ESD protection of high frequency circuits in sub-100nm bulk CMOS technologies, “ in Proc EOS/ESD Symposium, pp. 4A.2-1 4A.2-7, 2007 19 J. Di Sarro, K. Chatty, R. Gauthier, E. Rosenbaum, “Evaluation of

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24、ulk CMOS Technologies, “ in Proc International Reliability Physics Symposium, pp. 163-168, 2006 21 M. Mergens, O. Marichal, S. Thijs, B. Van Camp, C. Russ, “Advanced SCR ESD protection circuits for CMOS/SOI nanotechnologies, “ in Proc Custom Integrated Circuits Conference, pp. 481-488, 2005. 22 Indu

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28、c Discharge Control Program for: Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive Devices) JEDEC Publication No. 157 Page 3 2 References (contd) 28 R. Gaertner, Do we expect ESD-failures in an EPA designed according to international

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49、scharge sensitive FA failure analysis FAR failure analysis report FCDM (FICDM) field-induced charged device model FCBM (FICBM) field-induced charged board model FIM field induced model FWHH full width at half height GND negative voltage supply HBM human body model HF high frequency HSS (HSSL) high speed serial link IC integrated circuit ICT in circuit test I/O input/output IEC International Electrotechnical Commission JEDEC Jo