DLA SMD-5962-96727 REV B-2001 MICROCIRCUIT DIGITAL CMOS BUS CONTROLLER MONOLITHIC SILICON《抗辐射互补金属氧化物半导体母线控制器硅单片电路数字微电路》.pdf

《DLA SMD-5962-96727 REV B-2001 MICROCIRCUIT DIGITAL CMOS BUS CONTROLLER MONOLITHIC SILICON《抗辐射互补金属氧化物半导体母线控制器硅单片电路数字微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-96727 REV B-2001 MICROCIRCUIT DIGITAL CMOS BUS CONTROLLER MONOLITHIC SILICON《抗辐射互补金属氧化物半导体母线控制器硅单片电路数字微电路》.pdf（15页珍藏版）》请在麦多课文档分享上搜索。

1、REVISIONSLTR DESCRIPTION DATE (YR -MO -DA) APPROVEDA Added Intersil as source of supply CAGE 34371. Updated boilerplate andeditorial changes throughout. LTG00-09-12 Monica L. PoelkingB Update boilerplate to MIL-PRF-38535 requirements. LTG 01-04-20 Thomas M. HessREVSHEETREVSHEETREV STATUS REV B A B B

2、 A A A A A A B A A BOF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14PMIC N/A PREPARED BY Thomas M. HessDEFENSE SUPPLY CENTER COLUMBUSSTANDARDMICROCIRCUITDRAWINGCHECKED BYThomas M. HessCOLUMBUS, OHIO 43216http:/www.dscc.dla.milTHIS DRAWING IS AVAILABLEFOR USE BY ALLDEPARTMENTSAPPROVED BYMonica L. Poe

3、lking MICROCIRCUIT, DIGITAL, CMOS, BUSCONTROLLER, MONOLITHIC SILICONAND AGENCIES OF THEDEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 96-02-23AMSC N/A REVISION LEVELBSIZEACAGE CODE67268 5962-96727SHEET 1 OF 14DSCC FORM 2233APR 97 5962 -E309-01DISTRIBUTION STATEMENT A . Approved for public release; dist

4、ribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA 5962-96727DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 2DSCC FORM 2234APR 971. SCOPE1.1 Scope . This drawing doc

5、uments two product assurance class levels consisting of high reliability (device classes Q and M)and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part orIdentifying Number (PIN). When available, a choice of Radiation Hardness

6、Assurance (RHA) levels are reflected in the PIN.1.2 PIN . The PIN is as shown in the following example:5962 - 96727 01 V R C Federal RHA Device Device Case Lead stock class designator type class outline fini shdesignator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / ( see 1.2.3)/ Draw

7、ing number1.2.1 RHA designator . Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and aremarked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix Aspecified RHA levels and are marked with the appropriate RHA d

8、esignator. A dash ( -) indicates a non -RHA device.1.2.2 Device type(s) . The device type(s) identify the circuit function as follows:Device type Generic number Circuit function01 82C88/7 Latchup resistant, CMOS, bus controller1.2.3 Device class designator . The device class designator is a single l

9、etter identifying the product assurance level as follows:Device class Device requirements documentationM Vendor self -certification to the requirements for MIL-STD-883 compliant, non -JANclass level B microcircuits in accordance with MIL-PRF-38535, appendix AQ or V Certification and qualification to

10、 MIL-PRF-385351.2.4 Case outline(s) . The case outline(s) are as designated in MIL-STD-1835 and as follows:Outline letter Descriptive designator Terminals Package styleR CDIP2-T20 20 Dual-in-line package1.2.5 Lead finish . The lead finish is as specified in MIL-PRF-38535 for device classes Q and V o

11、r MIL-PRF-38535,appendix A for device class M.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA 5962-96727DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 3DSCC FORM 2234APR 971.3 Absolute

12、 maximum ratings . 1 /Supply voltage (V CC ) . +8.0 V dcInput or I/O voltage range . GND 0.5 V dc to V CC +0.5 V dcStorage temperature range (T STG ) . -65 C to +150 CJunction temperature (T J ) . +175 CLead temperature (soldering 10 seconds) +265 CThermal resistance, Junction-to-case ( JC ) 12 C/WT

13、hermal resistance, Junction to ambient ( JA ) . 68 C/WMaximum package power dissipation T A = +125 C (P D ) 2 / 0.74 W1.4 Recommended operating conditions .Operating supply voltage range (V CC ) . 4.5 V dc to +5.5 V dcOperating temperature range (T A ) -55 C to +125 CInput low voltage range (V IL )

14、. 0.0 V dc to +0.7 V dcInput high voltage range, except clock pin (V IH ) . 2.2 V dc to V DDInput high voltage range, clock pin (V IHC ) V DD 0.8 V to V DD1.5 Digital logic testing for device classes Q and V . Fault coverage measurement of manufacturinglogic tests (MIL -STD -883, test method 5012) .

15、 90 percent2. APPLICABLE DOCUMENTS2.1 Government specification, standards, and handbooks . The following specification, standards, and handbooks form a part ofthis drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issueof the De

16、partment of Defense Index of Specifications and Standards ( DoDISS) and supplement thereto, cited in the solicitation.SPECIFICATIONDEPARTMENT OF DEFENSEMIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.STANDARDSDEPARTMENT OF DEFENSEMIL -STD -883 - Test Method Standard Mic

17、rocircuits.MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.HANDBOOKSDEPARTMENT OF DEFENSEMIL-HDBK-103 - List of Standard Microcircuit Drawing s.MIL -HDBK -780 - Standard Microcircuit Drawings.(Unless otherwise indicated, copies of the specification, standards, and handbooks are

18、available from the StandardizationDocument Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)1 / Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at themaximum levels may degrade performance and affect reliability.2 / If

19、device power exceeds package dissipation capabilit y provide heat sinking or derate linearly (the derating is based onJA ) at the rate of 14.7mW/ CProvided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA 5962-96727DEFENSE SUP

20、PLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 4DSCC FORM 2234APR 972.2 Order of precedence . In the event of a conflict between the text of this drawing and the references cited herein, the text ofthis drawing takes precedence. Nothing in this document, however, supersedes appl

21、icable laws and regulations unless a specificexemption has been obtained.3. REQUIREMENTS3.1 Item requirements . The individual item requirements for device classes Q and V shall be in accordance withMIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (

22、QM) plan. Themodification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for deviceclass M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein.3.2 Design, construction, and p

23、hysical dimensions . The design, construction, and physical dimensions shall be as specified inMIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.3.2.1 Case outline(s) . The case outline(s) shall be in accordance with 1.2.4 herein.3.2.2 Ter

24、minal connections . The terminal connections shall be as specified on figure 1.3.2.3 Block diagram . The block diagram shall be as specified on figure 2.3.2.4 Test circuit and timing waveforms . The test circuit and timing waveforms shall be as specified on figure 3.3.3 Electrical performance charac

25、teristics and postirradiation parameter limits . Unless otherwise specified herein, the electricalperformance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambientoperating temperature range.3.4 Electrical test requirements . The elect

26、rical test requirements shall be the subgroups specified in table IIA. The electrical testsfor each subgroup are defined in table I.3.5 Marking . The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be markedas listed in MIL-HDBK-103. For packages w

27、here marking of the entire SMD PIN number is not feasible due to space limitations, themanufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designatorshall still be marked. Marking for device classes Q and V shall be in accordance with MIL-

28、PRF-38535. Marking for device class Mshall be in accordance with MIL-PRF-38535, appendix A.3.5.1 Certification/compliance mark . The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required inMIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in

29、 MIL-PRF-38535, appendix A.3.6 Certificate of compliance . For device classes Q and V, a certificate of compliance shall be required from a QML -38535 listedmanufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate ofcompliance shall be

30、 required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see6.6.2 herein). The certificate of compliance submitted to DSCC -VA prior to listing as an approved source of supply for this drawi ngshall affirm that the manufacturers product meets, for device c

31、lasses Q and V, the requirements of MIL-PRF-38535 and herein orfor device class M, the requirements of MIL-PRF-38535, appendix A and herein.3.7 Certificate of conformance . A certificate of conformance as required for device classes Q and V inMIL-PRF-38535 or for device class M in MIL-PRF-38535, app

32、endix A shall be provided with each lot of microcircuits delivered tothis drawing.3.8 Notification of change for device class M . For device class M, notification to DSCC -VA of change of product (see 6.2 herein)involving devices acquired to this drawing is required for any change as defined in MIL-

33、PRF-38535, appendix A.3.9 Verification and review for device class M . For device class M, DSCC, DSCCs agent, and the acquiring activity retain theoption to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made availableonshore at the option of

34、 the reviewer.3.10 Microcircuit group assignment for device class M . Device class M devices covered by this drawing shall be in microcircuitgroup number 105 (see MIL-PRF-38535, appendix A).Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICR

35、OCIRCUIT DRAWINGSIZEA 5962-96727DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 5DSCC FORM 2234APR 97TABLE I. Electrical performance characteristics .Test SymbolConditions 1 /-55 C T A +125 Cunless otherwise specified Group Asubgroups Device type Limits UnitMin MaxLogi

36、cal “1” input voltage V IH V CC = 5.5 V 2 /Pins 1, 3, 6, 15, 18, 191, 2, 3 All 2.2 VLogical “0” input voltage V IL V CC = 4.5 V 2 /Pins 1, 3, 6, 15, 18, 191, 2, 3 All 0.7 VLogical “1” input voltage clock V IHC V CC = 5.5 V, Pin 2 2 / 1, 2, 3 All 4.7 VLogical “0” input voltage clock V ILC V CC = 4.5

37、V, Pin 2 2 / 1, 2, 3 All 0.8 VV OH1A V CC = 4.5 VI OH = -8.0 mAPins 4, 7, 8, 9, 11-143.0Output high voltageV OH1B V CC = 4.5 VI OH = -2.5 mAPins 4, 7, 8, 9, 11-141, 2, 3 AllV CC-0.4VV OH2A V CC = 4.5 VI OH = -4.0 mAPins 4, 5, 16, 173.0Output high voltageV OH2B V CC = 4.5 VI OH = -2.5 mAPins 4, 5, 16

38、, 171, 2, 3 AllV CC-0.4VOutput low voltage V OL1 V CC = 4.5 VI OL = +12.0 mAPins 4, 7, 8, 9, 11-141, 2, 3 All 0.5 VOutput low voltage V OL2 V CC = 4.5 VI OL = +8.0 mAPins 4, 5, 16, 171, 2, 3 All 0.4 VInput leakage current I IHI ILV CC =5.5 V, V IN = GND orV CC , Pins 1, 2, 6, 151, 2, 3 All -1.0 1.0

39、AOutput leakage current I OZLI OZHV CC = 5.5 VV OUT = GND or V CCPins 7, 8, 9, 11-141, 2, 3 All -10.0 10.0 AStandby power supply current I CCSB V CC = 5.5 V, V IN = GND orV DD , Outputs open1, 2, 3 All 10.0 AOperating power supplycurrentI CCOP V CC = 5.5 V, V IN = GND orV DD , Outputs open,f= 10 MHz

40、1, 2, 3 All 10.0 mAInput leakage current statusbusI BHH V CC = 5.5 V 3 /Outputs open, Pins 3,18,191, 2, 3 All -300 -50.0 AInput capacitance C IN 4 All 13.0 pFOutput capacitance C OUTV CC = Open, f = 1 MHzAll measurementsreferenced to GNDSee 4.4.1c4 All 20.0 pFFunctional tests V CC = 4.5 V and 5.5 VS

41、ee 4.4.1b7, 8 AllSee footnotes at end of table.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA 5962-96727DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 6DSCC FORM 2234APR 97TABLE I. El

42、ectrical performance characteristics Continued.Test SymbolConditions 1 /-55 C T A +125 Cunless otherwise specified Group Asubgroups Device type Limits UnitMin MaxTIMING REQUIREMENTSCLK cycle period t CLCL 9, 10, 11 All 125.0 nsCLK low time t CLCH 9, 10, 11 All 55.0 nsCLK high time t CHCL 9, 10, 11 A

43、ll 45.0 nsStatus active setup time t SVCH 9, 10, 11 All 35.0 nsStatus inactive setup time t CHSV 9, 10, 11 All 10.0 nsStatus active hold time t SHCL 9, 10, 11 All 35.0 nsStatus inactive hold time t CLSHV CC = 4.5 V and 5.5 VSee figure 3 2 /9, 10, 11 All 10.0 nsControl active delay t CVNV 9, 10, 11 A

44、ll 5.0 45.0 nsControl inactive delay t CVNXV CC = 4.5 V and 5.5 VSee figure 3Condition 1 9, 10, 11 All 10.0 45.0 nsALE active delay from CLK t CLLH 9, 10, 11 All 20.0 nsMCE active delay from CLK t CLMCH 9, 10, 11 All 25.0 nsALE active delay from status t SVLH 9, 10, 11 All 20.0 nsMCE active delay fr

45、om status t SVMCH 9, 10, 11 All 30.0 nsALE inactive delay t CHLLV CC = 4.5 V and 5.5 VSee figure 3 2 /Condition 19, 10, 11 All 4.0 22.0 nsCommand active delay t CLML 9, 10, 11 All 5.0 35.0 nsCommand inactive delay t CLMHV CC = 4.5 V and 5.5 VSee figure 3 2 /Condition 2 9, 10, 11 All 5.0 35.0 nsDirec

46、tion control active delay t CHDTL 9, 10, 11 All 50.0 nsDirection control inactivedelayt CHDTHV CC = 4.5 V and 5.5 VSee figure 3 2 /Condition 1 9, 10, 11 All 30.0 nsCommand enable time t AELCH V CC = 4.5 V and 5.5 VSee figure 3 2 / 4 /Condition 39, 10, 11 All 40.0 nsCommand disable time t AEHCZ V CC

47、= 4.5 V and 5.5 VSee figure 3 5 /Condition 49, 10, 11 All 40.0 nsEnable delay time t AELCV V CC = 4.5 V and 5.5 VSee figure 3 2 /Condition 29, 10, 11 All 110.0 250.0 nsAEN to DENt AEVNV 9, 10, 11 All 25.0 nsCEN to DEN, PDENt CEVNVV CC = 4.5 V and 5.5 VSee figure 3 2 /Condition 1 9, 10, 11 All 25.0 n

48、sDEN to command t CELRH V CC = 4.5 V and 5.5 VSee figure 3 2 /Condition 29, 10, 11 All t CLML+10nsALE high time t LHLL V CC = 4.5 V and 5.5 VSee figure 3 2 /Condition 19, 10, 11 All t CLML-10ns1 / All testing to be performed using worst-case test conditions unless otherwise specified.2 / These test are verified functionally as Go/no Go test.3 / I BHH should be measured after raising the V IN on S0, S1, S2 to V CC and then lowering to 2.0 V.4 / t AELCH me