DLA SMD-5962-88726 REV F-2010 MICROCIRCUIT MEMORY DIGITAL CMOS ULTRAVIOLET ERASABLE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added two device types with access times of 25 ns and 20 ns for vendor CAGE 1FN41. Added low power version. Added F-16 package. Editorial changes throughout. 92-04-21 M. A. Frye B Source for 01, 02, and 06 devices no longer available. Added devic

2、es 08-12. Added 28 J leaded chip carrier package. Updated boilerplate, editorial changes throughout. 94-10-21 M. A. Frye C Updated to new boilerplate format. Added new footnote to ICC1 in table I, renumbered the rest of footnotes. Added additional conditions to ICC1 conditions block. Changed the max

3、 limit for devices 11 and 12 for ICC2 from 5 mA to 15 mA. 00-02-22 Raymond Monnin D Made changes to table I for device type 08; tSS, fMAXS, and tSFS. Updated boilerplate, editorial changes throughout. ksr 02-09-06 Raymond Monnin E Boilerplate update, part of 5 year review. ksr 07-06-22 Robert M. Heb

4、erF Made changes to “Margin test method” in paragraph 4.2c, added footnote 7/ to Table I for parameter “Clock to feedback”, and changed the maximum capacitance in Table I; CIfrom 8 to 20 pF and COfrom 8 to 15 pF. ksr 10-03-17 Charles F. Saffle REV SHET REV F F F F F F F F SHEET 15 16 17 18 19 20 21

5、22 REV STATUS REV F F F F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLUMBUS, OHIO 43218-3990http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL

6、 DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS, ULTRAVIOLET ERASABLE, PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88 09 - 16 AMSC N/A REVISION LEVEL F SIZE A CAGE CODE 67268 5962-88726 SHEET 1 OF 22 DSCC F

7、ORM 2233 APR 97 5962-E213-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88726 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope.

8、This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88726 01 L A _ Drawing number Device type Case out

9、line Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Address access time 01 V750 22-input 10-output 40 ns and-or-logic array 02 V750 22-input 10-output 35 ns and-or-logic ar

10、ray 03 V750 22-input 10-output 25 ns and-or-logic array 04 V750 22-input 10-output 20 ns and-or-logic array 06 V750L 22-input 10-output 35 ns and-or-logic array 07 V750L 22-input 10-output 25 ns and-or-logic array 08 V750B 22-input 10-output 10 ns and-or-logic array 09 V750B 22-input 10-output 15 ns

11、 and-or-logic array 10 V750B 22-input 10-output 25 ns and-or-logic array 11 V750BL 22-input 10-output 15 ns and-or-logic array 12 V750BL 22-input 10-output 25 ns and-or-logic array 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive

12、 designator Terminals Package style L GDIP3-T24 24 dual-in-line package 1/ 3 CQCC1-N28 28 square chip carrier 1/ X GDFP1-F24 24 flat pack package 1/ Y CQCC1-J28 28 J leaded chip carrier 1/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. _ 1/ Lid shall be transparent

13、to permit ultraviolet light erasure. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88726 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute

14、maximum ratings. 2/ Supply voltage range -0.5 V dc to +7.0 V dc Input voltage range . -2.0 V dc to +7.0 V dc 3/ Output voltage applied -0.5 V dc to +7.0 V dc 3/ Output sink current . 16 mA Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Maximum power dissipation (PD) 4/ 1.2 W Maximum junc

15、tion temperature +175C Lead temperature (soldering, 10 seconds maximum) . +300C 1.4 Recommended operating conditions. Supply voltage (VCC) . 4.5 V dc to 5.5 V dc High level input voltage (VIH) 2.0 V dc minimum Low level input voltage (VIL) 0.8 V dc maximum 2. APPLICABLE DOCUMENTS 2.1 Government spec

16、ification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PR

17、F-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircui

18、t Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event

19、of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individua

20、l item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted tr

21、ansitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requir

22、ements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. _ 2/ All voltages r

23、eferenced to VSS. 3/ Minimum voltage is -0.6 V dc which may undershoot to -2.0 V dc for pulses of less than 20 ns. Maximum output pin voltage is VCC+0.75 V dc which may overshoot to +7.0 V dc for pulses of less than 20 ns. 4/ Must withstand the added PDdue to short circuit test, e.g., IOS. Provided

24、by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88726 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 4 DSCC FORM 2234 APR 97 3.2 Design, construction, and physical dimensions. The desi

25、gn, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table(s).

26、The truth table(s) shall be as specified on figure 2. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in group A, B, or C inspections (see 4.3), the device shall be programmed by t

27、he manufacturer prior to test with a minimum of 50 percent of the total number of gates programmed or to any altered item drawing pattern which includes at least 25 percent of the total number of gates programmed. 3.2.3.2 Programmed devices. The requirements for supplying programmed devices are not

28、part of this drawing. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperatu

29、re range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PI

30、N listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance

31、 indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Processing EPLDS. All testi

32、ng requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.6.1 Erasure of EPLDS. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.4. 3.6.2 Programmability of EPLDS. When specified, de

33、vices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5 and table III. 3.6.3 Verification of erasure of programmability of EPLDS. When specified, devices shall be verified as either programmed to the specified pattern or erased. As a minimum, veri

34、fication shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.7 Certificate of compliance. A certificate of compliance

35、 shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL

36、-PRF-38535, appendix A and the requirements herein. 3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.9 Notification of change. Notification of change to DSCC-VA shall be

37、 required for any change that affects this drawing. 3.10 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the re

38、viewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88726 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteri

39、stics Test Symbol Conditions 1/ 4.5 V VCC 5.5 V -55C TC +125C Unless otherwise specified Group A Subgroups Device types Limits Unit Min Max High level output voltage VOHIO= - 4.0 mA 1,2,3 All 2.4 V Low level output voltage VOLIO= 8.0 mA 1,2,3 01-04, 06, 07 0.5 V IO= 12 mA 08-12 High impedance 2/ out

40、put leakage current IOZVCC= 5.5 V, VO= 5.5 V, VO= GND 1,2,3 All -10 10 uA High level input current IIHVIH= 5.5 V 1,2,3 All 10 uA VIH= 2.4 V 1,2,3 All 10 Low level input current IILVIH= 0.4 V 1,2,3 All -10 uA VIH= GND 1,2,3 All -10 Operating supply current ICC1 VCC= 5.5 V, f = 1MHz, Outputs open, VIN

41、= VCCor GND 3/ 1,2,3 01-04, 06, 07 140 mA 08-12 190 Standby supply current ICC2VCC= 5.5 V, VIN= GND, outputs open 1,2,3 01-04 140 mA 08-10 190 06, 07 15 11,12 15 Output short 4/ circuit current IOSVCC= 5.5 V 1,2,3 All -30 120 mA Input capacitance CI5/ 6/ VI= 0 V, VCC= 5.0 V, TA= 25C, f = 1 MHz (see

42、4.3.1c) 4 All 20 pF Output capacitance CO5/ 6/ VO= 0 V, VCC= 5.0 V, TA= 25C, f = 1 MHz (see 4.3.1c) 4 All 15 pF Functional tests see note 4 of table II 7, 8A, 8B See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD

43、MICROCIRCUIT DRAWING SIZE A 5962-88726 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ 4.5 V VCC 5.5 V -55C TC+125C unless otherwise specified Group A subgroup

44、sDevice Limits Unit Min MaxInput or feedback to nonregistered output tPDVCC= 4.5 V, CL= 50 pF, see figures 4 and 5 9, 10, 11 01 40 ns02 35 06 30 03, 07, 10, 12 25 04 20 08 10 09, 11 15 Clock to output tCOVCC= 4.5 V , CL= 50 pF, see figures 4 and 5 9, 10, 11 01 35 ns 02,06 30 03,07 10,12 22 04 20 09,

45、11 14 08 10 Input to output enable tEAVCC= 4.5 V , CL= 5 pF, see figures 4 and 5 9, 10, 11 01 40 ns 02,06 35 03,07, 10,12 25 04 20 09,11 15 08 10 Input to output disable tER9, 10, 11 01 40 ns 02,06 35 03,07, 10,12 25 04 20 09,11 15 08 10 See footnotes at end of table. Provided by IHSNot for ResaleNo

46、 reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88726 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions

47、 1/ 4.5 V VCC 5.5 V -55C TC+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Clock period tPVCC= 4.5 V , CL= 5 pF, see figures 4 and 5 9, 10, 11 01 35 ns 02,06 30 03,07 22 04 18 10,12 17 09,11 14 08 11 Clock pulse width 5/ 6/ tCLVCC= 4.5 V , CL= 50 pF, see figures 4

48、and 5 9, 10, 11 01 17 ns 02,06 15 03,07 10 10,12 8.5 04 8 09,11 7 08 5.5 Clock to feedback 7/ tCF9, 10, 11 01 15 ns 02,06 12 03, 04,07, 10,12 10 09,11 9 087.5 Input setup time 5/ 6/ tSVCC= 4.5 V , CL= 50 pF, see figures 4 and 5 9, 10, 11 01 20 ns 02,06 18 03,07, 10,12 12 04,11 10 09 8 08 4 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted withou