DLA SMD-5962-01508 REV H-2013 MICROCIRCUIT MEMORY DIGITAL CMOS FIELD PROGRAMMABLE GATE ARRAY 32 000 GATES MONOLITHIC SILICON.pdf

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1、REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes made to Table 1, updated paragraph 4.4.1f, and editorial changes throughout. Ksr 03-02-21 Raymond Monnin B Added tR and tF to section 1.4, and updated boilerplate paragraphs. Ksr 04-03-12 Raymond Monnin C Added devices 05 - 08, Update to 1

2、.3, made changes to IIL and IOZ in Table I, made change to paragraph 4.2.2 and 4.4.1f, and updated boilerplate paragraphs. Ksr 04-08-27 Raymond Monnin D Add case outline Z, in section 1.3 change input voltage range max number from 5.5 V to 6.0 V, added statements to sections 4.3 and 4.4, and added c

3、ase outline Z to figure 1 and figure 2. ksr 05-10-05 Raymond Monnin E Boilerplate update, part of 5 year review. ksr 10-11-15 Charles F. Saffle F Added device types 09 and10 to section 1.2.2 and Table I. Added case Z to JC in 1.3. Revised Case outline Z in Figure 1. Added additional testing criteria

4、 for devices 09 and 10 in 4.4.2.2 and 4.4.5. Removed reference to a vendor internal document in 4.4.1f(2). Added 4.4.5. Removed reference to vendor software in 4.6. Removed vendor website URL from 6.7. Updated boilerplate to current requirements. lhl 12-05-21 Charles F. Saffle G Updated boilerplate

5、to current requirements. Removed Class M references. Section 4.2.2 is now 4.2.1. Updated section 4.2.1.e for device types 09 and 10. lhl 12-11-26 Charles F. Saffle H Updated boilerplate to current requirements. Updated section 4.2.1e(7) for device types 09 and 10. 13-12-12 Charles F. Saffle REV SHEE

6、T REV H H H H H H H H H H SHEET 15 16 17 18 19 20 21 22 23 24 REV STATUS REV H H H H H H H H H H H H H H OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING

7、CHECKED BY Raj Pithadia THIS DRAWING IS AVAILABLE FOR USE BY ALL APPROVED BY Raymond Monnin MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 32,000 GATES, MONOLITHIC SILICON DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 01-07-30 AMSC N/A REVISION LEVE

8、L H SIZE A CAGE CODE 67268 5962-01508 SHEET 1 OF 24 DSCC FORM 2233 APR 97 5962-E068-14 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01508 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SH

9、EET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Num

10、ber (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 01508 01 Q X C | | | | | | | | | | | | | | | | | | Federal RHA Device Device Case Lead stock class designator type class outline fin

11、ish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA devi

12、ce. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 RT54SX32S 32,000 gate field programmable gate array 02 RT54SX32S-1 32,000 gate field programmable gate array 1/ 03 RT54SX32S 32,000 gate field programmable gate array

13、 2/ 04 RT54SX32S-1 32,000 gate field programmable gate array 1/ 3/ 05 RTSX32SU 32,000 gate field programmable gate array 06 RTSX32SU-1 32,000 gate field programmable gate array 1/ 07 RTSX32SU 32,000 gate field programmable gate array 4/ 08 RTSX32SU-1 32,000 gate field programmable gate array 1/ 5/ 0

14、9 RTSX32SU 32,000 gate field programmable gate array 6/ 10 RTSX32SU-1 32,000 gate field programmable gate array 1/ 7/ 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or

15、V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 256 Ceramic Quad Flat Pack Y See figure 1 208 Ceramic Quad Flat Pack Z See figu

16、re 1 84 Ceramic Quad Flat Pack 1/ Timing performance of the RT54SX32S-1 and RTSX32SU-1 devices shall be approximately 15% faster than the RT54SX32S and RTSX32SU devices (End users may select the appropriate device speed grade through timing calculations based on timing simulation of specific designs

17、 with manufacturers Designer software.) (see 6.7 herein) 2/ Device type 03 is device type 01 with additional testing (see 4.2.1 e) 3/ Device type 04 is device type 02 with additional testing (see 4.2.1 e) 4/ Device type 07 is device type 05 with additional testing (see 4.2.1 e) 5/ Device type 08 is

18、device type 06 with additional testing (see 4.2.1 e) 6/ Device type 09 is device type 05 with additional testing (see 4.2.1.e) 7/ Device type 10 is device type 06 with additional testing (see 4.2.1.e) Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-S

19、TANDARD MICROCIRCUIT DRAWING SIZE A 5962-01508 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 3 DSCC FORM 2234 APR 97 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q. 1.3 Absolute maximum ratings (for 2.5V/3.3V/5.0V operating condition

20、s). 8/ DC supply voltage range (VCCI) . -0.3 to +6.0 V dc DC supply voltage range (VCCA) -0.3 to +3.0 V dc Input voltage range (VI) -0.5 to +6.0 V dc Input voltage(VI) for bi-directional I/Os when using 3.3V PCI -0.5 to (+VCCI +0.5) V dc Output voltage range (VO) -0.5 to (+VCCI +0.5) V dc Storage te

21、mperature range (VSTG) -65C to +150C Lead temperature (soldering, 10 seconds) . 300C Thermal resistance, junction-to-case (JC for Case X, Y and Z) . 2.0C/W Maximum junction temperature (TJ) . 150C 1.4 Recommended operating conditions. 3.3V power supply voltage range . 3.0 to 3.6 V dc (10% VCCI) 5.0V

22、 power supply voltage range . 4.5 to 5.5 V dc (10% VCCI) 2.5V power supply voltage range . 2.25 to 2.75 V dc (10% VCCA) Case operating temperature range (TC) . -55C to +125C Input transition time TR and TF 10 ns 9/ 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of m

23、anufacturing logic tests (MIL-STD-883, test method 5012) 100 percent 10/ 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the i

24、ssues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Stan

25、dard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk,

26、 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 8/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 9/ If TR and TF exceeds the limit of 10 ns, the device manu

27、facturer cannot guarantee device functionality. 10/ 100 percent test coverage of blank programmable logic devices. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01508 DLA LAND AND MARITIME COLUMBUS, OHIO 43

28、218-3990 REVISION LEVEL H SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. JEDEC SOL

29、ID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC JESD 78 - IC Latch-Up Test. (Copies of this document are available online at www.jedec.org/ or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201). (Non-Government standards and other publications are

30、normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, th

31、e text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF

32、-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions s

33、hall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). 3.2.3.1 Unprogr

34、ammed devices. The truth table or test vectors for unprogrammed devices for contracts involving no altered item drawing is not part of this drawing. When required in screening (see 4.2 herein) or qualification conformance inspection, groups A, B, C, D, or E (see 4.4 herein), the devices shall be pro

35、grammed by the manufacturer prior to test. A minimum of 90 percent of the total number of logic modules shall be utilized or at least 25 percent of the total logic modules shall be utilized for any altered item drawing pattern. 3.2.3.2 Programmed devices. The truth table or test vectors for programm

36、ed devices shall be as specified by an attached altered item drawing. 3.2.4 Switching test circuit and waveforms. The switching test circuit and waveforms diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise spec

37、ified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA.

38、The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufac

39、turer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q a

40、nd V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01508 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 5 DSCC FORM 2234 APR 97

41、3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listin

42、g as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall b

43、e provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01508 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 6 DSCC FORM 22

44、34 APR 97 TABLE I. Electrical performance characteristics. 1/ 2/ Operation with VCCI = 3.3V or VCCI = 5.0V (for 3.3V LVTTL and 5V TTL I/O Operations) Test Symbol Conditions 3/ 2.25 V VCCA 2.75 V 3.0 V VCCI 3.6 V or 4.5 V VCCI 5.5 V -55C TC +125C unless otherwise specified Group A subgroups Device ty

45、pe Limits Unit Min Max High level output voltage VOH VCCI = Min., VI = VIH or VIL IOH = -1 mA 1,2,3 All 0.9 VCCI V VCCI = Min., VI = VIH or VIL IOH = -8 mA 2.4 Low level output voltage VOL VCCI = Min., VI = VIH or VIL IOL = 1 mA 1,2,3 All 0.1 VCCI V VCCI = Min., VI = VIH or VIL IOH = 12 mA 0.40 Low

46、level input voltage VIL 1,2,3 All 0.8 V High level input voltage VIH 1,2,3 All 2.0 V Input leakage current IIL VIN = VCCI or GND 1,2,3 01,02, 03,04 -20 20 A VIN = VCCI or GND and 4.5 V VCCI 5.25 V 05,06, 07,08, 09, 10 -20 20 A VIN = VCCI or GND and 5.25 V VCCI 5.5 V 05,06, 07,08, 09, 10 -70 70 A 3-s

47、tate output leakage current IOZ VOUT = VCCI or GND 1,2,3 01,02, 03,04 -20 20 A VIN = VCCI or GND and 4.5 V VCCI 5.25 V 05,06, 07,08, 09, 10 -20 20 A VIN = VCCI or GND and 5.25 V VCCI 5.5 V 05,06, 07,08, 09, 10 -70 70 A I/O terminal capacitance CI/O the latter includes FRAME#, IRDY#, TRDY#, DEVSEL#,

48、STOP#, SERR#, PERR#, LOCK#, and, when used AD63:32, C/BE7:4#, PAR64, REQ64#, and ACK64#. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01508 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 10 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. 1/ 2/ 10/ Absolute maximum pin capacitance for a PCI input is 10 pF. Exceptions