DLA DSCC-VID-V62 12614 REV A-2012 MICROCIRCUIT LINEAR DIFFERENCE AMPLIFIER HIGH COMMON MODE VOLTAGE MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add tube option under paragraph 6.3. - ro 12-08-06 C. SAFFLE Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY RICK OFFICER DLA
2、LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, LINEAR, DIFFERENCE AMPLIFIER, HIGH COMMON MODE VOLTAGE, MONOLITHIC SILICON 12-04-17 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12614 REV A PAGE 1 O
3、F 12 AMSC N/A 5962-V089-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12614 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high p
4、erformance high common mode voltage difference amplifier microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control numbe
5、r for identifying the item on the engineering documentation: V62/12614 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 INA149-EP High common mode voltage difference amplifier 1.2.2 Case out
6、line(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 8 MS-012-AA Plastic small surface mount 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Mater
7、ial A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12614 REV A PAGE 3 1.3 Absolute
8、 maximum ratings. 1/ Supply voltage range (+VSto -VS) . 40 V Input voltage range (continuous) 300 V Common mode and differential, 10 seconds 500 V Maximum voltage on REFA and REFB -VS 0.3 V to +VS+ 0.3 V Input current on any input pin . 10 mA 2/ Output short circuit duration . Indefinite Junction te
9、mperature range (TJ) +150C Storage temperature range (TSTG) -65C to +150C Electrostatic discharge (ESD) rating: Human body model (HBM) . 1500 V Charged device model (CDM) 1000 V Machine model (MM) . 100 V 1.4 Recommended operating conditions. 3/ Supply voltage range (+VSto -VS) . 15 V Operating free
10、-air temperature range (TA) . -55C to +125C 1.6 Thermal characteristics. Thermal metric Symbol Case X Unit Thermal resistance, junction-to-ambient 4/ JA110 C/W Thermal resistance, junction-to-case (top) 5/ JC(TOP)57 C/W Thermal resistance, junction-to-board 6/ JB54 C/W Characterization parameter, ju
11、nction-to-top 7/ JT11 C/W Characterization parameter, junction-to-board 8/ JB53 C/W 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
12、those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ REFA and REFB are diode clamped to the power supply rails. Signal applied to these pins that can swing more than 0.3 V beyond
13、the supply rails should be limited to 10 mA or less. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ The thermal resi
14、stance, junction-to-ambient under natural convection is obtained in a simulation on a JEDEC standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 5/ The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the package top. No
15、 specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 6/ The thermal resistance, junction-to-board is obtained by simulating in an environment with a ring cold plate fixture to control the printed circuit board (PCB) temperature, as described in
16、 JESD51-8. 7/ Characterization parameter, junction-to-top (JT) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 8/ Characterization parameter, junction-to-board (JB
17、) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MA
18、RITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12614 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices EIA/JESD51-2a - Integrated Circuits Thermal Test Method Environment Conditions N
19、atural Convection (Still Air) EIA/JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages EIA/JESD51-8 - Integrated Circuits Thermal Test Method Environment Conditions Junction-to-Board (Applications for copies should be addressed to the Electronic Industries Alli
20、ance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) ANSI SEMI STANDARD G30-88 - Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semicon
21、ductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers nam
22、e, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and ele
23、ctrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure
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