DLA DSCC-VID-V62 12611-2012 MICROCIRCUIT DIGITAL-LINEAR OCTAL 24 BIT ANALOG TO DIGITAL CONVERTER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE 18 19 20 21 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of

2、 drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, DIGITAL-LINEAR, OCTAL, 24 BIT, ANALOG TO DIGITAL CONVERTER, MONOLITHIC SILICON 12-08-16 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12611 REV PAGE 1 OF 21 AMSC N/A 5962-V037-12 Provided by IHSNot for ResaleNo

3、 reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12611 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance octal 24 bit analog to digital converter microcir

4、cuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/

5、12611 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 ADS1278-EP Octal 24 bit analog to digital converter 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter

6、Number of pins JEDEC PUB 95 Package style X 64 MS-026 Plastic quad flat pack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash

7、palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12611 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Analog power supply (AVDD) to analog ground (AGND) . -0.3

8、 V to 6.0 V Digital power supply (DVDD), Digital power supply (IOVDD) to digital ground (DGND) -0.3 V to 3.6 V AGND to DGND . -0.3 V to 0.3 V Input current: Momentary . 100 mA Continuous . 10 mA Analog input to AGND -0.3 V to AVDD + 0. 3 V Digital input or output to DGND -0.3 V to DVDD + 0.3 V Stora

9、ge temperature range (TSTG) -60C to +150C 1.4 Recommended operating conditions. 2/ Operating free-air temperature range (TA) . -55C to +125C 1.5 Thermal characteristics. Thermal metric Symbol Case X Unit Thermal resistance, junction-to-ambient 3/ JA33.1 C/W Thermal resistance, junction-to-case JC6.2

10、 C/W Thermal resistance, junction-to-board 4/ JB7.9 C/W Characterization parameter, junction-to-top 5/ JT0.2 C/W Characterization parameter, junction-to-board 6/ JB7.8 C/W _ 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress rat

11、ings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Use of this product beyond the manuf

12、acturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 3/ The thermal resistance, junction-to-ambient under natural convection is obtained in a simulation on a JEDEC

13、standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 4/ The thermal resistance, junction-to-board is obtained by simulating in an environment with a ring cold plate fixture to control the printed circuit board (PCB) temperature, as described in JESD51-8. 5/ Cha

14、racterization parameter, junction-to-top (JT) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 6/ Characterization parameter, junction-to-board (JB) estimates the j

15、unction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS,

16、OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12611 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices EIA/JESD51-2a - Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (

17、Still Air) EIA/JEDEC 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages EIA/JESD51-8 - Integrated Circuits Thermal Test Method Environment Conditions Junction-to-Board (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson

18、 Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identifica

19、tion (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3,

20、 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shal

21、l be as shown in figure 2. 3.5.3 Timing waveforms. The timing waveforms shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12611 REV PAGE 5 TABLE

22、 I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Full scale input 3/ voltage FSR VIN= AINP - AINN -55C to +125C 01 VREF typical V Absolute input voltage AINP or AINN to AGND -55C to +125C 01 AGND 0.1 AVDD + 0.1 V Common mode input

23、 voltage VCMVCM= (AINP + AINN) / 2 -55C to +125C 01 2.5 typical V Difference input High speed mode -55C to +125C 01 14 typical k impedance High resolution mode 14 typical Low power mode 28 typical Low speed mode 140 typical DC performance Resolution NO missing codes -55C to +125C 01 24 Bits Data rat

24、e fDATAHigh speed mode, 4/ fCLK= 32.768 MHz -55C to +125C 01 128,000 typical SPS Measured in samples per seconds (SPS) High speed mode, fCLK= 27 MHz 105,469 typical SPS 5/ High resolution mode 52,734 typical SPS Low power mode 52,734 typical Low speed mode 10,547 typical Integral nonlinearity 6/ INL

25、 Differential input, VCM= 2.5 V -55C to +125C 01 0.0014 %FSR 3/ Offset error -55C to +125C 01 2 mV Offset drift -55C to +125C 01 0.8 typical V/C Gain error -55C to +125C 01 0.5 %FSR Gain drift -55C to +125C 01 1.3 typical ppm / C See footnotes at end of table. Provided by IHSNot for ResaleNo reprodu

26、ction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12611 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Noise High

27、speed mode, shorted input -55C to +125C 01 68 V, High resolution mode, shorted input 13 rms Low power mode, shorted input 21 Low speed, shorted input 21 Common mode rejection ratio CMRR fCM= 60 MHz -55C to +125C 01 90 dB Power supply rejection ratio PSRR AVDD, fPS= 60 Hz -55C to +125C 01 80 typical

28、dB DVDD, fPS= 60 Hz 85 typical IOVDD, fPS= 60 Hz 105 typical VCOM output voltage No load -55C to +125C 01 AVDD/2 typical V AC performance Crosstalk f = 1 kHz, -0.5 dBFS 7/ -55C to +125C 01 -107 typical dB Signal to noise ratio 8/ SNR High speed mode -55C to +125C 01 88.3 dB (unweighted) High resolut

29、ion mode, VREF= 2.5 V 101 High resolution mode, VREF= 3 V 111 typical Low power mode 98 Low speed mode 98 Total harmonic 9/ distortion THD VIN= 1 kHz, -0.5 dBFS -55C to +125C 01 -96 dB Spurious free dynamic range -55C to +125C 01 109 typical dB Passband ripple -55C to +125C 01 0.005 typical dB Passb

30、and -55C to +125C 01 0.453 fDATAtypical Hz -3 dB bandwidth -55C to +125C 01 0.49 fDATAtypical Hz See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V

31、62/12611 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max AC performance continued. Stop band attenuation High resolution mode -55C to +125C 01 95 dB All other modes 100 Stop band High resolution mode -

32、55C to +125C 01 0.547 fDATA127.453 fDATAHz All other modes 0.547 fDATA63.453 fDATAGroup delay High resolution mode -55C to +125C 01 39 / fDATAtypical s All other modes 38 / fDATAtypical Settling time (latency) High resolution mode, complete settling -55C to +125C 01 78 / fDATA typical s All other mo

33、des, complete settling 76 / fDATAtypical Voltage reference inputs. Reference input voltage, VREF= VREFfCLK= 27 MHz -55C to +125C 01 0.5 3.1 V VREFP - VREFN fCLK= 32.768 MHz 4/ 0.5 2.6 Negative reference input VREFN -55C to +125C 01 AGND 0.1 AGND + 0.1 V Positive reference input VREFP -55C to +125C 0

34、1 VREFN + 0.5 AVDD + 0.1 V Reference input impedance High speed mode -55C to +125C 01 0.65 typical k High resolution mode 0.65 typical Low power mode 1.3 typical Low speed mode 6.5 typical See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without lic

35、ense from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12611 REV PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Digital input / output. (IOVDD = 1.8 V to 3.6 V). Inpu

36、t high voltage VIH-55C to +125C 01 0.7 IOVDD IOVDD V Input low voltage VIL-55C to +125C 01 DGND 0.3 IOVDD V Output high voltage VOHIOH= 4 mA -55C to +125C 01 0.8 IOVDD IOVDD V Output low voltage VOLIOL= 4 mA -55C to +125C 01 DGND 0.2 IOVDD V Input leakage 0 27 MHz, operation is limited to frame sync

37、 mode and VREF 2.6 V. 5/ SPS = samples per second. 6/ Best fit method. 7/ Worst case channel crosstalk between one or more channels. 8/ Minimum SNR is ensured by the dc noise limit. 9/ THD includes the first nine harmonics of the input signal; low speed mode includes the first five harmonics. 10/ Ti

38、ming parameters are characterized or guaranteed by design for specified temperature but, not production tested. 11/ fCLK= 27 MHz maximum. 12/ Depends on MODE (1:0) and CLKDIV selection. See Table II. 13/ Load on DRDY and DOUT = 20 pF. 14/ For best performance, limit fSCLK/ fCLKto ratios of 1, 1/2, 1

39、/4, 1/8, etc. 15/ tDOHD(DOUT hold time) and tDIHD(DIN hold time) are specified under opposite worst case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4 ns. 16/ SCLK must be continuously running and limi

40、ted to ratios of 1, 1/2, 1/4, and 1/8 of fCLK. 17/ Load on DOUT = 20 pF. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12611 REV PAGE 13 Case X FIGURE 1. Case outline. Pro

41、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12611 REV PAGE 14 Case X Symbol Dimensions Inches Millimeters Min Max Min Max A - 0.047 - 1.20 A1 0.037 0.047 0.95 1.05 A2 0.009

42、 - 0.25 - A3 0.001 0.005 0.05 0.15 b 0.006 0.010 0.17 0.27 c 0.005 nominal 0.13 nominal D/E 0.295 typical 7.50 typical D1/E1 0.385 0.401 9.80 10.20 D2/E2 0.464 0.480 11.80 12.20 e 0.019 BSC 0.50 BSC L 0.017 0.029 0.45 0.75 NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given fo

43、r reference only. 2. Body dimensions do not include mold flash or protrusion. 3. This package is designed to be soldered to a thermal pad on the board. Refer to technical brief, power pad thermally enhanced package, manufacturer literature number SLMA002 for information regarding recommended board l

44、ayout. This document is available from the manufacturer. 4. Falls within reference to JEDEC MS-026. FIGURE 1. Case outline - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 D

45、WG NO. V62/12611 REV PAGE 15 Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 AINP2 17 DOUT4 2 AINN2 18 DOUT3 3 AINP1 19 DOUT2 4 AINN1 20 DOUT1 5 AVDD 21 DGND 6 AGND 22 IOVDD 7 DGND 23 IOVDD 8 TEST0 24 DGND 9 TEST1 25 DGND 10 CLKDIV 26 DVDD 11 SYNC 27 C

46、LK 12 DIN 28 SCLK 13 DOUT8 29 DRDY /FSYNC 14 DOUT7 30 FORMAT2 15 DOUT6 31 FORMAT1 16 DOUT5 32 FORMAT0 FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG

47、 NO. V62/12611 REV PAGE 16 Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 33 MODE1 49 AINP6 34 MODE0 50 AINN6 35 PWDN8 51 AINP5 36 PWDN7 52 AINN5 37 PWDN6 53 AVDD 38 PWDN5 54 AGND 39 PWDN4 55 VCOM 40 PWDN3 56 VREFP 41 PWDN2 57 VREFN 42 PWDN1 58 AGND 43 AGND 59 AGND 44 AVDD 60 AVDD 45 AINP8 61 AINP4 46 AINN8 62 AINN4 47 AINP7 63 AINP3 48 AINN7 64 AINN3 FIGURE 2. Terminal connections - Continued. Provided by IHSNot for ResaleNo reproduction or net