Assessing Chip-Level Impact of Double Patterning Lithography.ppt

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1、Assessing Chip-Level Impact of Double Patterning Lithography,Kwangok Jeong*, Andrew B. Kahng*,*, and Rasit O. Topaloglu*http:/vlsicad.ucsd.edu/* ECE Dept., UC San Diego * CSE Dept., UC San Diego * GlobalFoundries, Inc.,Outline,Double Patterning Lithography (DPL) Traditional Interconnect Analysis Add

2、itional Variability in DPL Misalignment in Double Patterning Analysis in Different DPL Options Experiments Conclusion,Outline,Double Patterning Lithography (DPL) Traditional Interconnect Analysis Additional Variability in DPL Misalignment in Double Patterning Analysis in Different DPL Options Experi

3、ments Conclusion,Double Patterning Lithography (DPL),Pattern-doubling: 2X-resolution lithography with 1X-resolution equipmentTaxonomy Resist type: positive /negative Methods: double exposure (DE) / double patterning (DP) / spacer double patterning (SDP) Printed feature: line / space,Traditional Inte

4、rconnect Analysis,Designers use capacitance tables from foundries2D/3D field solver with variations Capacitance tables Major sources of variation: Metal/dielectric density-dependent systematic variation Random process variation Results of variation Width (W) variation Metal height (H) variation Diel

5、ectric thickness (D) variation, etc.,Traditional interconnect variation analysis,1. for (i = -3 ; i 3 ; i=i+1) for (j = -3 ; j 3 ; j=j+1) for (k = -3 ; k 3 ; k=k+1) W=Wnom + iWH= Hnom + jHD= Dnom + kDrun field solver over parameterized structureFind nominal and worst-case capacitance,Additional Vari

6、ability in DPL,Overlay error Causes: mask misalignment material stress-impacted deformations litho-/etch-impacted topography lens aberration, etc. Impacts on DPL Width variation Space (or pitch) variation Capacitance variation,Alignment metricIndirect: Two DPL masks aligned to a reference layer Erro

7、r: Direct: Second DPL mask aligned to the first DPL mask Error:,Indirect Alignment (IA),Cc,Cg,Direct Alignment (DA),Outline,Double Patterning Lithography (DPL) Traditional Interconnect Analysis Additional Variability in DPL Misalignment in Double Patterning Analysis in Different DPL Options Experime

8、nts Conclusion,Misalignment in Positive DE/DP,Space on one side increases Space on the other side decreasesRequired design of experiments foreach S (-3 3)mask1 shift by +S/2mask2 shift by S/2 end,After exposure + etch,Cu filling,(misaligned to left),Misalignment in Negative DE/DP,1,2,1,2,1,W,W,S,S,P

9、,P,S/2,mask1,mask2 (misaligned to left),Negative photoresist,Dielectric,After exposure + etch,After filling Cu,Width of one increases Width of the other decreases Required design of experiments foreach S (-3 3)mask1 change W by +S shift by S/2mask2 change W by S shift by S/2 end,Spacer Thickness Var

10、iation in Positive SDP,Dielectric,(kind of) Positive photoresist,Spacers (act as if masks),Width and space change Required design of experiments foreach S (-3 3)mask1 change W by 0mask2 change W by +S end,Spacer Thickness Variation in Negative SDP,Primary patterns,Dielectric,After exposure + etch,Af

11、ter filling Cu,Spacers (act as if masks),(kind of ) Negative photoresist,Cu,Width and space change Required design of experiments foreach S (-3 3)mask1 change W by +S/2 shift by +S/4mask2 change W by +S/2 shift by S/4 end,Outline,Double Patterning Lithography (DPL) Traditional Interconnect Analysis

12、Misalignment in Double Patterning Analysis in Different DPL Options Experiments Conclusion,Photoresist,Process,Alignment,Experiments: Scenarios,We examine impact of misalignment and linewidth variation across various DPL options,Parallel 5-Interconnect Structure (TCAD tool),Interconnects in a full-c

13、hip (Signoff RCX),DE,DP,SDP,Direct,DE,DP,SDP,TCAD-Based BEOL Analysis Results,Capacitance variation due to misalignment in DE/DP IA shows larger variation than DA Negative resist processes have larger variation,Capacitance variation in different DPL options SDP has larger variation Negative resist p

14、rocesses have larger variation,Capacitance (aF/um),Capacitance (aF/um),Design-Level Analysis - Flow,Overlay-aware extraction flow,Overlay error can cause more than +/- 10% capacitance variation within a die, for all DPL options Large on-chip variation Increase of timing optimization difficulty,Capac

15、itance Variation (%),Design-Level Capacitance Variation,M2,M3,M4,M5,A net having maximum crosstalk delay (17um long) SDP shows more sensitivity tighten overlay spec P-DE/DP shows least sensitivity lessen overlay spec,Maximum Crosstalk-Induced Delay,Total Negative Slack Variation,SDP, especially for

16、lower layer (smaller feature), shows more sensitivity tighter overlay spec,TNS Variation (%),Outline,Double Patterning Lithography (DPL) Traditional Interconnect Analysis Misalignment in Double Patterning Analysis in Different DPL Options Experiments Conclusion,Summary of Observations,Overlay error

17、with indirect alignment (IA) results in higher capacitance variations compared to direct alignment (DA) Capacitance can vary 10% due to misalignment Large OCV increase timing optimization difficulty Timing can be degraded significantly, e.g., 10% worse TNS P-DE/DP may be the most favorable option fo

18、r BEOL DPL With the same 3 overlay control, the variation in P-DE/DP is 50% of N-DE/DP or P-SDP, and 25% of N-SDP Overlay control spec for P-DE/DP can be relaxed by 2X compared to others,Conclusion and Ongoing Work,We provide a variational interconnect analysis framework for double patterning lithog

19、raphy We analyze mechanisms of interconnect variations due to misalignment and spacer thickness variation in DPL We provide both interconnect and design-level RC-extraction framework reflecting interconnect variation in a 45nm DPL process We compare the impact of overlay error in different DPL optio

20、ns Ongoing work Development of timing analysis and optimization methodology considering interconnect variation in DPL Incorporation of statistical techniques to target pessimism reduction,Thank You!,Impact of Misalignment on FEOL,Standard cell decompositionExperimental setup 10nm 3 misalignment is a

21、ssumed between layers Design of experiments (all permutation: 3*3*3*3 = 81 cases) P1: -10nm (L) / 0nm (C) / +10nm (R) P2: -10nm (L) / 0nm (C) / +10nm (R) M: -10nm (L) / 0nm (C) / +10nm (R) C: -10nm (L) / 0nm (C) / +0nm (R),Experimental Results on FEOL,FlowImpact of misalignment on cell delay is negl

22、igibly small ( 2%) Capacitance variation due to misalignment gate capacitance,Measured Delay Variation (%),Tr-level RC-Extraction,STAR-RCXT,Circuit Simulation,HSPICE,DPL Options,Double Exposure,Double Patterning,Spacer-DP,Photoresist,Printed Feature,Mask Coloring and Layout Examples in DPL,Mechanism

23、 of misalignment-induced variation,(a) DE and DP Process,(b) SDP Process,Original patterns,Original patterns,Coloring,Patterns 1,Patterns 2,Coloring,Spacer formation (Large spacer),Trim & repair (dark gray),S,S,Narrow space,W,W”,Dummy for pattern 6,1,4,5,2,3,6,Spacer (gray),a,b,Design-Level Analysis

24、 - DOE,Design of Experiments for DE/DP with DA,foreach layer M2, M3, M4, M5 decompose layer into layermask1 and layermask2foreach S -3/2, -2/2, -/2, 0, /2, 2/2, 3/2 shift layermask1 by Sshift layermask2 by Sendlayer layermask1 + layermask2foreach W -3/2, -2/2, -/2, 0, /2, 2/2, 3/2resize layer by W e

25、ndmerge with other layersRC-Extraction and Timing Analysisend,Impact on Capacitance Variation,Total interconnect capacitance: maximum C(%) Among top 20% high capacitance nets Impact of overlay impact of widthSum of capacitance in the most critical path Critical path has short interconnects impact of

26、 BEOL variation significantly reduces Impact of overlay impact of width,Impact on Crosstalk-Induced Delay,Maximum coupling induced delay change PrimeTime-SI (Synopsys) is used to find a net that is mostly affected due to crosstalk Temporal/functional filtering is performed Selected net structureA ne

27、t with relatively small length (17um) can have 10% delay changes due to overlay error,Capacitance when Delay is minimum,Capacitance when Delay is maximum,Impact on Timing,Longest path and total negative slack (TNS)Impact of overlay impact of widthLongest path delay changes negligiblyHowever, overall timing (TNS) can change significantly,Total Negative Slack (ns),