DLA SMD-5962-96747-1997 MICROCIRCUIT DIGITAL ADVANCED CMOS SCAN PATH SELECTOR WITH 8-BIT BIDIRECTIONAL DATA BUS TTL COMPATIBLE INPUTS MONOLITHIC SILICON《双极的互补金属氧化物半导体 8-BIT双向的数据总线扫.pdf

《DLA SMD-5962-96747-1997 MICROCIRCUIT DIGITAL ADVANCED CMOS SCAN PATH SELECTOR WITH 8-BIT BIDIRECTIONAL DATA BUS TTL COMPATIBLE INPUTS MONOLITHIC SILICON《双极的互补金属氧化物半导体 8-BIT双向的数据总线扫.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-96747-1997 MICROCIRCUIT DIGITAL ADVANCED CMOS SCAN PATH SELECTOR WITH 8-BIT BIDIRECTIONAL DATA BUS TTL COMPATIBLE INPUTS MONOLITHIC SILICON《双极的互补金属氧化物半导体 8-BIT双向的数据总线扫.pdf（32页珍藏版）》请在麦多课文档分享上搜索。

1、LTR DESCRIPTION DATE (YR-MO-DA) REV 111 APPROVED SHEET I 15 I 16 I 17 CHECKED BY Thanh V. Nguyen - APPROVED BY Monica L. Poelking DRAWING APPROVAL DATE 97-03-1 8 REVISION LEVEL REV STATUS OF SHEETS COLUMBUS, OHIO 43216 MICROCIRCUIT, DIGITAL, ADVANCED CMOS, SCAN PATH SELECTOR WITH 8-BIT BIDIRECTIONAL

2、 DATA BUS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON 59 62-9 6747 SIZE CAGE COOE A 67268 SHEET 1 OF 31 PMIC NIA STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A PREPAREDBY Thanh V. Nguyen I DEFENSE SUPPLY CENTER, CO

3、LUMBUS )ESC FORM i93 JUL 94 DISTRIBUTION STATFMF m. Approved for public release; distribution is unlimited. 5962-327-95 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SID-5962-9b47 W 9979996 0094905 118 W 1. SCOPE 1 .I m. This drawing documents two

4、product assurance dass levels consisting of high reliability (device classes Q and M) and space application (device dass V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). Men available, a choice of Radiation Hardness Assurance RH

5、A) levels are reflected in the PIN. I QorV Certification and qualification to MIL-PRF-38535 1.2.4 Case -. The cases outline are as designated in MIL-STD-1835 and as follows: I Temiinals EiadwWm X GDIPCT28 28 Dual-in-line package I 3 CQCC1 -N28 28 Square chip carrier 1.2.5 -. The lead finish is as sp

6、edied in MIL-PRF-38535 for device dasses Q and V or MIL-PRF-38535, appendix 1 A for device dass M. 1.2 m. The PIN is as shown in the following example: Federal RHA 96747 I_ Device 1 Device 1 Case i Lead ILL stock class designator type class outline finish designator (see 1.2.1) L I (see 1.2.3) (see

7、1.2.5) (see 1.2.2) designator (see 1.2.4) v Drawing number 1.2.1 PHAdes ianator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator, Device dass M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA

8、 levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 . The device type identifies the circuit function as follows: -nction O1 54ACT8999 Scan path selector with 8-bit bidirectional data bus, TTL compatible inputs 1.2.3 follows: . The device class de

9、signator is a single letter identifying the product assurance level as M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class levei 8 microcircuits in accordance with MIL-PRF-38535, appendix A I 696246747 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reprodu

10、ction or networking permitted without license from IHS-,-,- SND-5962-967Y7 = 9999996 OO9490b 054 = 1.3 Absolute max mum rat inm. 11 21 31 . -0.5 V dc to +7.0 V dc -0.5 V dc to Vcc +0.5 V dc 41 . -0.5 V dc to VCc +0.5 Vdc d/ I20 mA . 120 m S?5 mA . -65C to +1WC DC output damp Continuous output curren

11、t, Storage temperature range Lead temperature +3WC Thermal resistance, junction-to-case (OJc) . See MIL-STD-1835 Junction temperature fl ) . +175“ C Maximum power dissipafion (PD) . 85 mW 31 Minimum high level inp uFc voltage (Vi ) +2.0 V Maximum low level input voitage (V,j . +0.8 V Output voltage

12、range Po T) +O.O V dc to Vcc 1.4 Recommendmm- i . y 31 Supply voltage range (V Input voitage range (V ) . +O.O V dc to Vcc . +4.5 V dc to +5.5 V dc Maximum high level outpuycurrent (IoH): ID (1-8) . -1.6 mA TDO, DTDO, MCO - . -8.5 mA DTMS (I+, DCO (three-state), DTRST, DTCK . -13.6 mA ID (1-8) . +1.

13、6 KIA TDO, DTDO, MCO +8.5 mA lXWT;. DTMSm, DCO, DTCK 1 3020 Output current high, DCO (open drain) SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43216 REVISION LEVEL 0962-96747 SHEET 6 - vcc - 4.5 v - 4.5 v - 4.5 v - 4.5 v - 4.5 v - 4.5 v - 4.5 v - 4.5 v - 5.5 v

14、- 5.5 v - 5.5 v - - Symbol Test conditions 2/ unless otherwise specified -55C s TC 5 +125“C +4.5 v - TMSiL PAUSE-IR A I I I I FIGURE 4. Test access mrt CO ntroller and scan test m. I 5962-96747 REVISION LEVEL SHEET STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43216 DE

15、SC FORM 1931 JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-96747 9999996 0094924 07T Instruction register (IR) order of scan 4OTE: The MSB of theiELhm even-panty bit. If the value scanned into the IfUuth reset condition count up). S

16、top counting up counting down to 00000000 (control register bit Il ; reset conditon = do not latch on zero). Output Edge of DCI on which to trigger (control register bit 4; reset condition = positive edge). - signal at DCO (control register bits 8 and 9; reset conditon = do not output CE at DCO). Re

17、mote-test-port instruction-register opcodes I 01111110 1 SCANSEL I Select-registerscan I Select 1 I Bypa= I All other BYPASS Bypass scan Bit 1 in the control register allows a remote bus controller (RBC) to control parts of the device. When an RBC is enabled, the remote test port (RTP) in the select

18、 register is activated. The RTP does not have access to the control register, so it cannot disable itself. The primary bus controller (PBC) must reset bit 1 in the control register to return control of the select register to the primary test port. An internal error signai$WERR) is generated if an RB

19、C loads an invalid value in the seled d the MCO output goes low if the RSRERR is active and the remote TAP enters the pause-DR state. The RSRERR function table is shown in figure 2 herein. FIGURE 4. Test access mrt wnt roller and scan - Continued. STANDARD S962-96747 MICROCIRCUIT DRAWING DEFENSE SUP

20、PLY CENTER, COLUMBUS COLUMBUS, OHIO 43216 REVISION LEVEL DESC FORM 19% JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-96747 = 9999996 0094930 373 SIZE STANDARD A MICROCIRCUIT DRAW1 NG L DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO

21、43216 REVISION LEVEL INPUT OUTPUT OUTPUT 598296747 SHEET 27 3.0 V 0.0 v OH TCK 1.5 v OUTPUT 0.5 vcc v OL 3.0 V 0.0 V OH 2: GNO TCK 1.5 v OR DCI OUTPUT 0.5 Vcc 3.0 V 1.5 V 0.0 v * “cc TCK OR DCI 0.5 Vcc OVTPUT VOL JOTE: VHz = 0.9 V for ID-bus pins and VHz = 0.8 Vcc for all other pins. Vu = 0.1 VcC fo

22、r ID-bus pins and VE = 0.2 VEEfor all other pins. FIGURE 5. Switchina wavefor-nd test c ira. DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-I SMD-5962-96797 7797776 007473L 20T SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPL

23、Y CENTER, COLUMBUS COLUMBUS, OHIO 43216 I REVISION LEVEL 3.0 v 1.5 v 0.0 v 3.0 v TCK 1.5 v 0.0 v DATA INPUT 1 /“ *L tS-t-th 5962-96747 SHEET 28 LOW-HIGH-LOW PULSE 0.0 v 3.0 v 0.0 v H I GH - PULSE LOW- “ Ir )- 1.5 v P - PULSE * UNDER 4 * TEST GENERATOR RL RL NOTES: 1. = open. 3. When measuring tpH an

24、d tpZH: = 0.0 V. 4. The tpZL and tpE reference waveform IS for the output under test with intemal conditions such that the output is at V PRR 5 10 MHz; tr = 3.0 ns; t = 3.0 nc; 1, and +shall be measured from 0.3 V to 2.7 V and from 2.7 V to 0.3 V, respectively; duty cycle = 50 percent. 9. Timing par

25、ameters shall be tested at a minimum input frequency of 1 MHz. ?O. The outputs are measured one at a time with one transition per measurement. When measuring tpu and tpZL: V EST = Vcc for ID-bus pins and VTEsT = 2 x Vcc for all other pins. 2. When measuring tpLH and tpHL: T except when disabled by t

26、he output enable control. The tp and t reference waveform is for the output under exces when $%led by the output enable control. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-96747 m 9999996 0094932 146 m I Subgroups (in accordance with MI

27、L-STD-883, method 5005, table I) Device class M TABLE II. Flectrical tes t teouir-. Subgroups (in accordance with MlL-PRF-38535, table I I I) Device Device class Q class V Test Interim electrical parameters (see 4.2) parameters (see 4.2) requirements (see 4.4) parameters (see 4.4) parameters (see 4.

28、4) parameters (see 4.4) Final electrical Group A test Group C end-point electrical Group D end-point electrical 1 Group E end-point electrical requirements 1 -_ - Il 1,2,3,7,8,9, Il 1,2,3,7, a 1,2,3,7, 10, Il 8, 9. IO, II 8,9, 10, 11 1,2,3,7,8,9,10,11 1,2,3,7,8,9, 1,2,3,7,8, 10,ll 9, 10, 11 1,2,3 1,

29、2,3 I, 2,3,7,8, 9,10, 11 1,2,3 1,2,3 1,2,3 1, 7,9 1,7, 9 1,7,9 4. QUALITY ASSURANCE PROVISIONS 4.1 Samol na and insDect ion. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturers Quality Management (QM) pla

30、n. The modification in the QM plan shall not affect the form, ffi, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF38535, appendix A. on all devices prior to qualification and technology conformance inspection. For device cla

31、ss M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MlL-PRF-38535, and shall be conducted 4.2.1 wonal &a for dev ice cla

32、ss M. a. Bum-in test, method 1015 of MIL-STD-883. (I) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring adiviy upon request. The test circuit shall specify the inputs,

33、 outputs, biases, and power dissipation, as applicable, in accordance with the intent specified il test method 1015. (2) TA = +125”C, minimum. Interim and final electrical test parameters shall be as specified in table II herein. b. 5962-96747 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER, COL

34、UMBUS COLUMBUS, OHIO 4321 6 REVISION LEVEL DESC FORM 19% JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-9b747 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43216 W 9999996 0094933 O82 A 5962-96747 REVIS

35、ION LEVEL SHEET 30 4.2.2 Additional criteria for device classes Q a nd V. a. The bum-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturets QM plan in accordance with MIL-PRF-38535. The bum-in test Circuit shall be maintained

36、 under document revision level control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as app

37、licable, in accordance with the intent specified in test method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II herein. c. Additional screening for device class V beyond the requirements of device dass Q shall be as specified in MIL-PRF-38535, a

38、ppendix B. 4.3 Qualification insoection for de vice classes Q V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, 6, C, O, and E inspections (see 4.4.1 through

39、 4.4.4). performed in accordance with MIL-STD-883, method 3015. ESDS testing shall be measured only for initial qualification and after process or design changes which may affect ESDS classification. 4.4 Confo- insrect ion. Technology conformance inspection for classes Q and V shall be in accordance

40、 with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-PRF-38535 permits alternate in-line control testing. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein

41、. Inspections to be performed for device class M shall be those specified in method 5005 of M1L-STD-883 and herein for groups A, BI C, D, and E inspections (see 4.4.1 through 4.4.4). 4.3.1 Elect rostatic discharae sens itivitv qyalification imion . Electrostatic discharge sensitivity (ESDS) testing

42、shall be 4.4.1 Groui A insbection. a. Tests shall be as specified in table II herein. b. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth tables in figure 2 herein. The test vectors used to verity the truth tables shall, at a minimum, test all functions of each inp

43、ut and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth tables in figure 2, herein. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device: these tests shall have been fault graded in acco

44、rdance with MIL-STD-883, test method 5012 (see I .5 herein). capacitan$!%, and Cg For CIN and COUT, test alyapplicable pins on five devices with zero failures. 4.4.2 C inspect ion. The group C inspection end-point electrical parameters shall be as specified in table II herein. 4.4.2.1 -ria for devic

45、e c. CIN and C shall be measured only for initial qualification and after process or design changes which may affect shall be measured between the designated terminal and GND at a frequency of 1 MHz. . Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition A, B, Cl or D. Th

46、e test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test Circuit shall spec* the inputs, outputs, biases, and power dissipation. as applicable, in accordance with the intent

47、specified in test method 1005 Of MIL-STD-883. b. TA = +125“C, minimum. c. Test duration: I ,O00 hours, except as permitted by method 1005 of MIL-STD-883. . The steady-state lice test duration, test condition and test temperature, 4.4.2.2 Additignal ma for device classes Q and V or approved alternati

48、ves shall be as specified in the device manufacturers QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturers TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activi

49、ty upon request. The test circuit shall specfy the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. I SIZE I I DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-