JEDEC JESD8-19-2006 POD18 - 1 8 V Pseudo Open Drain I O《POD18-1 8V开漏电路I O》.pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD8-19DECEMBER 2006JEDECSTANDARDPOD18 - 1.8 V Pseudo Open DrainI/O NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Council level and subsequently reviewed and approved by the EIA Genera

2、lCounsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchaser in selecting and obtaining with minimum delaythe pr

3、oper product for use by those other than JEDEC members, whether the standard is to be usedeither domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption mayinvolve patents or articles, materials, or processes. By such action JEDEC

4、 does not assume anyliability to any patent owner, nor does it assume any obligation whatever to parties adopting theJEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from th

5、e solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publicationshould be addressed to JEDEC Solid State

6、 Technology Association, 2500 Wilson Boulevard,Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2006 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge, however JEDEC retains the copyright on th

7、is material. By downloading this file the individual agrees not to charge for or resell the resulting material. Price: Please refer to the current Catalog of JEDEC Engineering Standards and Publications at www.jedec.org Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This doc

8、ument is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association

9、 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 8-19Page 1POD18 - 1.8 V PSEUDO OPEN DRAIN I/O (From JEDEC Board Ballot JCB-06-27, formulated under the cognizance of the JC-16 Committee on Interface Technology.)1 ScopeThis standard defines the dc and ac

10、 single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.8 V Pseudo Open Drain I/Os. The 1.8 V Pseudo Open Drain interface, also known as POD18, is primarily used to communicate with GDDR3 SGRAM devices. 2 Operating conditio

11、nsTable 1 DC Electrical Characteristics and Operating ConditionsParameter Symbol Min Typ Max UnitSupply Voltage VDD 1.7 1.8 1.9 VI/O Supply Voltage VDDQ 1.7 1.8 1.9 VI/O Reference Voltage VREF 0.69 * VDDQ 0.70 * VDDQ 0.71 * VDDQ VInput High (Logic 1) Voltage VIH (DC) VREF + 0.15 VInput Low (Logic 0)

12、 Voltage VIL (DC) VREF 0.15 VInput Leakage CurrentAny Input 0V = VIN= VDD(All other pins not under test = 0V) Il 5 5 AOutput Leakage Current (DQs are disabled; 0V = Vout = VDDQ)Ioz 5 5 AOutput Logic LOW VOL (DC) 0.76 VTable 2 AC Input Operating ConditionsParameter Symbol Min Typ Max UnitInput High (

13、Logic 1) Voltage; DQ VIH (AC) VREF + 0.250 VInput Low (Logic 0) Voltage; DQ VIL (AC) VREF 0.250 VClock Input Differential Voltage; CK CK CK and CK# VMP (DC) 1.16 1.26 1.36 VClock Input Voltage Level; CK and CK# VIN(DC) 0.42 VDDQ + 0.3 VClock Input Differential Voltage ; CK and CK# VID (DC) 0.22 VDDQ

14、 VClock Input Differential Voltage ; CK and CK# VID (AC) 0.5 VDDQ + 0.5 VClock Input Crossing Point Voltage ; CK and CK# VIX (AC) VREF 0.15 0.70 * VDDQ VREF + 0.15 VCK#CKMaximum Clock Level 5Minimum Clock Level3VID(AC)4VID(DC)3VMP(DC)1VIX(AC)2JEDEC Standard No. 8-19Page 42 Operating conditions (cont

15、d)The Driver and Termination impedances are derived from the following test conditions under worst case process corners:1) Nominal 1.8V (VDD/VDDQ)2) Power the device and calibrate the output drivers however JEDEC retains the copyright on this material. By downloading this file the individual agrees

16、not to charge for or resell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved Rev. 9/02Standard Improvement Form JEDEC JESD8-19The purpose of t

17、his form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collected and dispersed to the appropriate committee(s).If you can provide input, plea

18、se complete this form (it can be edited in Acrobat Exchange) and return to:JEDECAttn: Publications Department2500 Wilson Blvd. Suite 220Arlington, VA 22201-3834Fax: 703.907.75831. I recommend changes to the following: Requirement, paragraph numberTest method number Paragraph numberThe referenced paragraph number has proven to be:Unclear Too Rigid In ErrorOther 2. Recommendations for correction:3. Other suggestions for document improvement:Submitted byName: Phone:Company: E-mail:Address: City/State/Zip: Date: