JEDEC JESD8-16A-2004 Bus Interconnect Logic (BIC) for 1 2 Volts《1 2V BIC的短系列终止逻辑(SSTL-3)》.pdf

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1、JEDEC STANDARD Bus Interconnect Logic (BIC) for 1.2 Volts JESD8-16A (Revision of JESD8-16) NOVEMBER 2004 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and sub

2、sequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser

3、in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or a

4、rticles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to pr

5、oduct specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI/EIA standard. No claims to be in conformance with thi

6、s standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid State

7、Technology Association 2004 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Please refer to t

8、he current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain pe

9、rmission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 8-16A Page 1 BUS INTERCONNECT LOGIC (BIC) FOR

10、1.2 V (From JEDEC Board Ballot JCB-04-101, formulated under the cognizance of the JC-16 Committee on Interface Technology.) 1 Scope This standard defines the input and output specifications for devices that are designed to operate in the BIC logic switching range, nominally 0 V to 1.2 V. The standar

11、d may be applied to ICs operating with separate VDD and VDDQ supply voltages; however, the VDD value is not specified in this standard. The standard also suggests bus configurations in which optimum performance may be gained. The standard defines the voltage thresholds, termination schemes, and test

12、 conditions for BIC compatibility. Class structures have been established to standardize output drive characteristics under various application conditions. Vendors may specify tighter tolerances on any or all parameters to increase performance. 2 Overview BIC is defined in both a differential form a

13、nd a single ended with VREF form. While the two versions have different signal requirements and are not fully interchangeable, they are compatible at the signal level and can be interconnected with minimal performance degradation. BIC is optimized for use with on die termination (ODT). In some appli

14、cations, this allows the components on the interface to be actively tuned for optimum performance and low noise under varying conditions. The single ended version has been optimized for parallel bus operation, requiring termination at both the source and receiver. It is expected that all termination

15、 will be on die, eliminating the need for external resistors, but external resistive components are compatible with BIC should the application require them. The differential version of BIC has been optimized for distributing clock signals or other very high-speed signals where signal integrity is cr

16、itical. Differential BIC can also be used for parallel busses, if the user can tolerate the extra signal lines required for differential signaling. This standard is a physical interface only and does not define training, or other potential bus architecture requirements, but BIC is fully compatible w

17、ith these if the user wishes to expand upon BIC capabilities. JEDEC Standard No. 8-16A Page 2 3 Standard specifications for single ended interfaces 3.1 Supply voltage levels Table 1 Supply voltage levels Symbol Parameter Min Nom Max Units Notes VDD Device supply voltage n/a n/a n/a V 1 VDDQ Output s

18、upply voltage 1.14 1.2 1.26 V VREF(dc) Input reference voltage 0.48 * VDDQ 0.5 * VDDQ 0.52 * VDDQ V 2 VREF(ac) Input reference voltage 0.47 * VDDQ 0.5 * VDDQ 0.53 * VDDQ V 2 VTT Termination voltage VDDQ/2 V 3 NOTE 1 Interface is not affected by device core voltage. NOTE 2 The referenced VDDQ is the

19、power supply voltage for the device receiving the VREF input. VREF (ac) is VREF (dc) plus noise. Peak to peak noise on VREF(ac) may not exceed 2% of VREF(dc). NOTE 3 The interface may be used with either ODT or external termination. The termination voltage VTT may either be supplied by an independen

20、t power supply or created through a Thevenin equivalent circuit. Regardless, the termination should be arranged for optimum signal integrity balanced at VDDQ/2 at the receiver. The min and max values should be set by the system designer to meet application needs. 3.2 Input voltage levels Table 2 Inp

21、ut voltage levels Symbol Parameter Min. Nom Max Units Notes VIH(dc) dc input high VREF + 0.08 VDDQ + 0.15 V 4, 6 VIL(dc) dc input low -0.15 VREF - 0.08 V 6 VIH(ac) ac input high VREF + 0.15 VDDQ + 0.24 V 4, 5, 6 VIL(ac) ac input low -0.24 VREF - 0.15 V 5, 6 NOTE 4 It is expected that most BIC compat

22、ible devices will utilize input clamp diodes, restricting the input voltage to the levels shown. For devices that have been specifically designed for hot insertion or power down on an active bus, the maximum input voltage shall be 1.26 V, regardless of the level of VDDQ. NOTE 5 The ac timing measure

23、ments, including propagation delays and setup/hold times will be measured beginning when the input signal crosses VREF. The ac overshoot above VDDQ and below VSS should not exceed 20% of the duty cycle of the signal, or exceed vendor specified limits. NOTE 6 For optimum noise margin and performance,

24、 the signal must maintain a center balance around VDDQ/2, VREF , and VTT, both at the driver and the receiver. Furthermore, VREF of the receiving device should track the variations in the dc value of the VDDQ of the sending device. JEDEC Standard No. 8-16A Page 3 3 Standard specifications for single

25、 ended interfaces (contd) 3.3 Devices with On Die Termination (ODT) The standard termination for BIC is a resistor (RT) at the end of the transmission line tied to a voltage level (VT) that is VDDQ. BIC devices may perform the termination function internally with On Die Termination (ODT) or external

26、ly with discrete devices. VT may be externally supplied, internally supplied, or generated through a Thevenin equivalent circuit within the device. If ODT is used, the parameters for specifying ODT as shown in Table 3 must be used. Table 3 BIC Input Impedance Parameters for Devices with Thevenin ODT

27、 Symbol Parameter Description Units Notes RT Termination impedance 7 RIL Specified input impedance when the input is logic low 8 RIH Specified input impedance when the input is logic high 9 RI Correlation between RIL and RIH % 10 NOTE 7 RT is the termination impedance. In order to identify differenc

28、es in the value of RT between input high and low conditions in ODT devices, the value of RT will be described and specified as RIL when the input is low and RIH when the input is high. Either RT or both RIL and RIH must be specified. It is not necessary to specify all three values. NOTE 8 RIL is the

29、 value of RT when ODT is active and the input is held at the nominal logic low position. The tested value of RIL must not exceed 15% of the specified value of RIL. NOTE 9 RIH is the value of RT when ODT is active and the input is held at the nominal logic high position. The tested value of RIH must

30、not exceed 15% of the specified value of RIH. NOTE 10 Ri = (actual RIH actual RIL) / (0.5 * (actual RIH + actual RIL). The correlation between RIL and RIH must not exceed 10%. 3.3.1 Testing devices with On Die Termination (ODT) The testing of ODT consists of forcing a current, and verifying that the

31、 input voltage falls within an expected range. This test is performed at the nominal logic high and low voltage levels. If the values of either RT or VT are outside of tolerances, one or both of the tests will fail. Table 4 shows the test condition limits for a BIC input with ODT turned on with 15%

32、impedance tolerance. The measured values of VIL and VIH must be used to calculate and guarantee RI. Table 4 Impedance test Limits Symbol Parameter and Condition Min Nom Max Unit VIL Input low, IIL = 0.25 * VDDQ / RIL 0.212 * VDDQ 0.25 * VDDQ 0.288 * VDDQ V VIH Input high, IIH = -0.25 * VDDQ / RIH 0.

33、712 * VDDQ 0.75 * VDDQ 0.788 * VDDQ V JEDEC Standard No. 8-16A Page 4 3.3 Devices with On Die Termination (ODT) (contd) 3.3.2 Applications information for ODT use with BIC (for reference only) When optimizing ODT for use in typical transmission line environments, the ODT impedance should be equal to

34、 or greater than the transmission line impedance for optimal performance. Setting the ODT impedance to match the transmission line impedance will avoid reflections in ideal applications. In less than ideal applications, losses, noise and other anomalies will degrade the signal on the transmission li

35、ne prior to the arrival at the ODT, making it desirable to slightly increase the impedance value of ODT to compensate. Increasing the value of ODT impedance will increase the edge rate of incoming signals in most applications, benefiting timing margins and accuracy. Implementation of ODT as a Theven

36、in circuit to VDDQ increases power dissipation by providing a current path directly through the pull up and pull down impedances from VDDQ to VSS. Increasing the ODT impedance of Thevenin implementations will reduce power consumption. Turning ODT off when the device is not receiving will also reduce

37、 power consumption in Thevenin implementations. This is especially true in bi-directional devices when the device is transmitting. Table 5 shows an example of an ODT specification for use in a 50 environment. In the example, the impedance is specified as both an RIL and RIH. The impedance is set at

38、55 to allow for losses and to provide a clean signal edge. In addition, the vendor would need to include a table similar to Table 4 to guarantee test limits. Table 5 Example of an ODT specification for a 50 W environment Symbol Parameter Description Value Units RT Termination impedance 55 RI Correla

39、tion between RIL and RIH 10 % RI = (RIH RIL) / (0.5 * (RIH + RIL) where RIH is RT measured at VI = 0.75 * VDDQ and RIL is RT measured at VI = 0.25 * VDDQ. Table 6 shows an example of an ODT specification for a device with adjustable input impedance. In the example, the impedance can be set at any va

40、lue from 55 to 85 . The vendor would also need to include a table similar to Table 4 to guarantee test limits. Table 6 Example of a specification for a device with variable ODT Symbol Parameter Description Min Max Units RIL Specified input impedance when the input is logic low 50 85 RIH Specified in

41、put impedance when the input is logic high 50 85 RI Correlation between RIL and RIH 10 % RI = (RIH RIL) / (0.5 * (RIH + RIL) where RIH measured at VI = 0.75 * VDDQ and RIL is measured at VI = 0.25 * VDDQ. JEDEC Standard No. 8-16A Page 5 3 Standard specifications for single ended interfaces (contd) 3

42、.4 Output characteristics It is intended that BIC outputs will be standard CMOS outputs with fairly linear impedance curves as shown in the VI diagrams in Figure 1. The left figure shows the desired pull down characteristics (ROL) and the right figure shows the desired pull up characteristics (ROH).

43、 Testing of ROL and ROH would be performed by forcing IOL and IOH, then verifying that VOL and VOH fall within the test limits as shown in Figures 1 and 2. The gray areas are the valid ranges for ROL and ROH. Current flowing into a device is considered positive current. Current flowing out of a devi

44、ce is considered negative current. Therefore, IOL is described as a positive value and IOH is described as a negative value.IOLROL ToleranceVOL(min)VOL(max)VDDQIOHROH ToleranceVOH(min)VOH(max) VDDQFigure 1 Idealized V/I curves for VOL and VOH measurements Most BIC outputs will limit output voltage t

45、o the values shown in Table 7. For devices that have been specifically designed for hot insertion into a powered system or power down on an active bus, the maximum output voltage shall be 1.26V, regardless of the level of VDDQ. The undefined values in Table 7 are characteristic of the device output

46、impedance and are defined by the class type in the following section. Table 7 Output voltage levels Symbol Parameter Min. Nom Max Units Notes VOH(dc) Output high voltage VDDQ + 0.15 V 11 VOL(dc) Output low voltage -0.15 V VOH(ac) Output high voltage VDDQ + 0.24 V 11, 12 VOL(ac) Output low voltage -0

47、.24 V 12 NOTE 11 Devices that have been designed for hot insertion or power down in an active system may allow voltages in excess of the maximum value. NOTE 12 The total ac overshoot above VDDQ and below VSS should not exceed 20% of the duty cycle of the signal, or exceed vendor specified limits. JE

48、DEC Standard No. 8-16A Page 6 3.4 Output characteristics (contd) 3.4.1 Output drive specifications BIC output drivers are defined in terms of the output impedance of the drivers and a tolerance on the output impedance. The maximum tolerance window on output impedance for BIC compliance has been set

49、at 15% of the specified impedance. Tighter tolerances may be specified by the vendor. Table 8 lists the three distinguishing parameters that define a BIC output class. These are the pull up impedance, the pull down impedance, and the tolerance between the two. Table 8 BIC output impedance parameters Symbol Parameter Description Units Notes ROL Specified output impedance when driving a logic low ROH Specified output impedance when driving a logic high R Correlation between ROL and ROH % 13 NOTE 13 R =