JEDEC JESD8-15A-2003 Stub Series Terminated Logic for 1 8 V (SSTL 18)《1 8V的短系列终止逻辑(SSTL-3)(SSTL－18)》.pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD8-15A SEPTEMBER 2003JEDECSTANDARDStub Series Terminated Logic for 1.8 V (SSTL_18) Addendum 15 to JESD8 Series(Revision of JESD8-15)NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Coun

2、cil level and subsequently reviewed and approved by the EIA GeneralCounsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting

3、 the purchaser in selecting and obtaining with minimum delaythe proper product for use by those other than JEDEC members, whether the standard is to be usedeither domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption mayinvolve

4、patents or articles, materials, or processes. By such action JEDEC does not assume anyliability to any patent owner, nor does it assume any obligation whatever to parties adopting theJEDEC standards or publications. The information included in JEDEC standards and publications represents a sound appr

5、oach to product specification and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met. Inquiries, comments, and suggestions relative to the content of this JED

6、EC standard or publicationshould be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard,Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2003 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be do

7、wnloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. Price: Please refer to the current Catalog of JEDEC Engineering Standards and Publications or call Global Engineering Docu

8、ments, USA and Canada (1-800-854-7179), International (303-397-7956) Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced without permission. Organizations may obtain permission

9、to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 8-15APage 1STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL

10、_18)(From JEDEC Board Ballots JCB-02-36, JCB-02-37, JCB-02-55, JCB-02-56, JCB-02-57, JCB-02-83, JCB-02-119, and JCB-03-40 formulated under the cognizance of the JC-16 Committee on Interface Technology.)1 ScopeThis standard defines the input, output specifications and ac test conditions for devices t

11、hat are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V. The standard may be applied to ICs operating with separate VDDand VDDQsupply voltages. The VDDvalue is not specified in this standard; however VDDand VDDQwill have the same voltage level in many cases.1.1 Stand

12、ard StructureThe standard is defined in four clauses:The first clause defines pertinent supply voltage requirements common to all compliant ICs.The second clause defines the minimum dc and ac input parametric requirements and ac test conditions for inputs on compliant devices.The third clause specif

13、ies the minimum required output characteristics of, and ac test conditions for, compliant outputs targeted for various application environments.The fourth clause specifies requirements for differential signaling.The full input reference level (VREF) range specified is required on each IC in order to

14、 allow any SSTL_18 integrated circuit to receive signals from any SSTL_18 output driver.1.2 Rationale and assumptionsThe SSTL_18 standard has been developed particularly with the objective of providing a relatively simple upgrade path from MOS push-pull interface designs. The standard is particularl

15、y intended to improve operation in situations where busses must be isolated from relatively large stubs. External resistors provide this isolation and also reduce the on-chip power dissipation of the drivers. Busses may be terminated by resistors to an external termination voltage.Actual selection o

16、f the resistor values is a system design decision and beyond the scope of this standard. However in order to provide a basis, the driver characteristics will be derived in terms of a typical 50 environment.While driver characteristics are derived from a 50 environment, this standard will work for ot

17、her impedance levels. The system designer will be able to vary impedance levels, termination resistors and supply voltage and be able to calculate the effect on system voltage margins. This is accomplished precisely because drivers and receivers are specified independently of each other. The standar

18、d defines a reference voltage VREFwhich is used at the receivers as well as a voltage VTTto which termination resistors are connected. In typical applications, VREFand VTTare nominally equal to VDDQ/2.JEDEC Standard No. 8-15APage 22 Supply voltage and input logic levelsThe standard defines both the

19、ac and dc input signal values. Making this distinction is important for the design of the high gain, differential receivers that are required. The ac values indicate the voltage levels at which the receiver must meet its timing specifications. The dc values indicate the voltage levels at which the f

20、inal logic state of the receiver is unambiguously defined. Once the receiver input has crossed the ac value, the receiver will change to the new logic state. The new logic state will then be maintained as long as the input stays beyond the dc threshold. This approach is intended to provide predictab

21、le receiver timing in the presence of input waveform “ringing”. The relationship of the different levels is shown in Figure 1. An example of ringing is illustrated in the waveform.Figure 1 SSTL_18 Input Voltage Levels2.1 Supply Voltage LevelsNOTE 1 The value of VREFmay be selected by the user to pro

22、vide optimum noise margin in the system. Typically the value of VREFis expected to be (50 +/- 1)% * VDDQof the transmitting device, e.g., VREFmin = 0.49 * VDDQmin and VREFmax = 0.51 * VDDQmax. VREFis expected to track variations in VDDQ.NOTE 2 Peak to peak ac noise on VREFmay not exceed +/- 2% of VR

23、EF(dc).NOTE 3 VTTis expected to track VREFof the receiving device.Table 1 Supply Voltage LevelsSymbol Parameter Min. Nom. Max. Units NotesVDDQOutput supply voltage 1.7 1.8 1.9 VVREFInput reference voltage 833 900 969 mV 1, 2VTTTermination voltage VREF- 40 VREFVREF+ 40 mV 3VDDQVIH(ac)VIH(dc)VREFVIL(d

24、c)VIL(ac)VSSJEDEC Standard No. 8-15APage 32.2 Input logic levelsNOTE 1 Within this standard, it is the relationship of the VDDQof the driving device and the VREFof the receiving device that determines noise margins. However, in the case of VIH(dc)max (i.e., input overdrive), it is the VDDQof the rec

25、eiving device that is referenced. In the case where a device is implemented that supports SSTL_18 inputs but has no SSTL_18 outputs (e.g., a translator), and therefore no VDDQsupply voltage connection, inputs must tolerate input overdrive to 2.2 V (VDDQmax + 300 mV).2.3 AC test conditionsThe ac inpu

26、t test conditions are specified to be able to obtain reliable, reproducible test results in an automated test environment, where a relatively high noise environment makes it difficult to create clean signals with limited swing. The tester may therefore supply signals with a 1.0 V peak to peak swing

27、to drive the receiving device. Note however, that all timing specifications are still set relative to the ac input level. This is illustrated in Figure 2.NOTE 1 Input waveform timing is referenced to the input signal crossing through the VREFlevel applied to the device under test. Table 1 identifies

28、 the VREFrange supported in SSTL_18.NOTE 2 Compliant devices must still meet the VIH(ac)and VIL(ac)specifications under actual use conditions.NOTE 3 The input signal minimum slew rate is to be maintained over the range from VIL(dc)max to VIH(ac)min for rising edges and the range from VIH(dc)min to V

29、IL(ac)max for falling edges as shown in Figure 2, consistent with the specifications of Tables 2 and 3. This is not a monotonicity requirement: ringing is still allowed as shown in Figure 1.NOTE 4 ac test conditions may be measured under nominal voltage conditions as long as the supplier can demonst

30、rate by analysis that the device will meet its timing specifications under all supported voltage conditions.Table 2 DC input logic levelsSymbol Parameter Min. Max. Units NotesVIH(dc)dc input logic high VREF+ 125 VDDQ+ 300 mV 1VIL(dc)dc input logic low -300 VREF- 125 mV 1Table 3 AC input logic levels

31、Symbol Parameter Min. Max. Units NotesVIH(ac)ac input logic high VREF+ 250 - mVVIL(ac)ac input logic low - VREF- 250 mVTable 4 AC input test conditionsSymbol Condition Value Units NotesVREFInput reference voltage 0.5 * VDDQV1, 4VSWING(MAX)Input signal maximum peak to peak swing 1.0 V 1, 2SLEW Input

32、signal minimum slew rate 1.0 V/ns 3JEDEC Standard No. 8-15APage 42.3 AC test conditions (contd)Figure 2 AC Input Test Signal Waveform3 SSTL_18 Output Buffers3.1 OverviewThis specification sets minimum requirements for output buffers such that when they are applied within the range of power supply vo

33、ltages specified in SSTL_18 and are used in conjunction with SSTL_18 input receivers, then the input receiver specifications can be met or exceeded. The specifications are quite different from traditional specifications, where minimum values for VOHand maximum values for VOLare set that apply to the

34、 entire supply range. In SSTL_18, the input voltage provided to the receiver depends on the driver as well as on the termination voltage and termination resistors. Figure 3 shows the typical dc environment that is presented to the output buffer.Figure 3 Typical output buffer (driver) environmentIn t

35、his environment, MOS output devices are deep into their triode region, so SSTL_18 driver characteristics are specified to ensure a driver output resistance (RON) no greater than 21 at the minimum VDDQ. It is understood that MOS devices are not perfectly linear, but designers are expected to scale up

36、 as needed to ensure that they meet the required operating points.VDDQVIH(ac)minVIH(dc)minVREFVIL(dc)maxVIL(ac)maxVSSVSWING(MAX)delta TRdelta TFStart of Falling Edge Input Timing Start of Rising Edge Input TimingVIH(dc)min - VIL(ac)maxdelta TFFalling Slew = Rising Slew = VIH(ac)min - VIL(dc)maxdelta

37、 TRVDDQVTTRTRS25 20 VREFVINVOUTVSSReceiverOutputBuffer(Driver)JEDEC Standard No. 8-15APage 53.2 SSTL_18 output buffers3.2.1 Push-pull output buffer for symmetrically double parallel terminated loads with series resistor (VTT= 0.5 * VDDQ)NOTE 1 VDDQ= 1.7 V; VOUT= 1420 mV. (VOUT- VDDQ)/IOHmust be less

38、 than 21 for values of VOUTbetween VDDQand VDDQ- 280 mV.NOTE 2 VDDQ= 1.7 V; VOUT= 280 mV. VOUT/IOLmust be less than 21 for values of VOUTbetween 0 V and 280 mV.NOTE 3 The dc value of VREFapplied to the receiving device is set to VTTNOTE 4 The values of IOH(dc)and IOL(dc)are based on the conditions g

39、iven in Notes 1 and 2. They are used to test device drive current capability to ensure VIHmin plus a noise margin and VILmax minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 lo

40、ad line to define a convenient driver current for measurement.3.2.2 SSTL_18 output ac test conditionsThis testing regimen is used to verify SSTL_18 output buffers (push-pull output buffers designed for symmetrically double parallel terminated loads with series resistor).This clause is added to set t

41、he conditions under which the driver ac specifications can be tested. The test circuit is assumed to be similar to the circuit shown in Figure 4. The ac test conditions may be measured under nominal voltage conditions as long as the supplier can demonstrate by analysis, that the device will meet its

42、 timing specifications under all supported voltage conditions. Table 6 assumes that 335 mV must be developed across the effectively 25 termination resistor at VIN(13.4 mA * 25 = 335 mV). With a series resistor of 20 this translates into a minimum requirement of 603 mV swing relative to VTT, at the o

43、utput of the device(13.4 mA * 45 = 603 mV).Table 5 Output dc current driveSymbol Parameter Min. Max. Units NotesIOH(dc)Output minimum source dc current -13.4 - mA 1, 3, 4IOL(dc)Output minimum sink dc current 13.4 - mA 2, 3, 4JEDEC Standard No. 8-15APage 63.2 SSTL_18 output buffers (contd)3.2.2 SSTL_

44、18 output ac test conditions (contd)Figure 4 Example of SSTL_18 symmetrically double parallel terminated output load with series resistorNOTE 1 The VDDQof the device under test is referenced.3.3 SSTL_18 noise marginSSTL_18 output devices are characterized for a linear 21 maximum output resistance (R

45、ON). The noise margin at the receiver under worst-case conditions is thus calculated as follows:Assume RS= 20 and RT= 25 .VDDQmin = 1.7 VVREFmin = 0.49 * VDDQmin = 833 mVVTT= VREFmin + 40 mV = 873 mVVIN= VTT* (RON+ RS)/(RON+ RS+ RT) = 873 mV * 41 / 66 = 542 mVVREF- VIN= 833 mV - 542 mV = 291 mVVIN(a

46、c)min = 250 mV (from Table 3).Table 6 AC Test ConditionsSymbol Condition Value Units NotesVOHMin. required output pull-up under ac test load VTT+ 603 mVVOLMax. required output pull-down under ac test load VTT- 603 mVVOTROutput timing measurement reference level 0.5 * VDDQmV 1VDDQVREF= 0.5 * VDDQVTT=

47、 0.5 * VDDQVOUTRS= 20 Z0= 50 VREF= 0.5 * VDDQRT2= 50 VSSDeviceundertestRT1= 50 VTT= 0.5 * VDDQJEDEC Standard No. 8-15APage 73.3 SSTL_18 noise margin (contd)As described, the receiver sees an input of 291 mV and only requires VIN(ac)min = 250 mV, for a gross margin of 41 mV. System designers may allo

48、cate this margin as judgment dictates. An SSTL_18 driver meeting these conditions while driving low would have the operating point:IOUT= IOL= (VTT- VIN)/RT= (873 mV - 542 mV) / 25 = 13.24 mAVOUT= VOL= VIN- IOUT* RS= 542 mV - 13.24 mA * 20 = 277.2 mVA similar calculation may be done for the case wher

49、e the receiver is driven high. In either case, the resulting values are shifted along a 21 load line to establish the output dc current drive requirements given in Table 5.4 Other applications (For reference only)The specifications for SSTL_18 are based on an environment comprising both series and parallel terminating resistors. In this non-binding section, some derived applications are shown. Clearly it is not the intention to show all possible variations in this standard.4.1 Push-pull output buffer for source