ATIS 0900105 08-2001 Synchronous Optical Network (SONET) C In-band Forward Error Correction Code Specification.pdf

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1、 AMERICAN NATIONAL STANDARD FOR TELECOMMUNICATIONS ATIS-0900105.08.2001(R2010) Synchronous Optical Network (SONET) In-band Forward Error Correction Code Specification ATIS is the leading technical planning and standards development organization committed to the rapid development of global, market-dr

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5、TANDARD Approval of an American National Standard requires review by ANSI that the requirements for due process, consensus, and other criteria for approval have been met by the standards developer. Consensus is established when, in the judgment of the ANSI Board of Standards Review, substantial agre

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10、action be taken periodically to reaffirm, revise, or withdraw this standard. Purchasers of American National Standards may receive current information on all standards by calling or writing the American National Standards Institute. Notice of Disclaimer this need for options is imposed by significan

11、t differences between network providers as well as between network elements. ANSI guidelines specify two categories of requirements: mandatory and advisory. The mandatory requirements are designated by the word “shall“ and the advisory criteria by the word “should.“ Mandatory requirements generally

12、apply to rate and format requirements by specifying absolute, acceptable minimum functionality in those areas; advisory requirements generally refer to optional features. There are two annexes in this standard. Both are informative and are not considered part of the standard. Suggestions for improve

13、ment of this standard are welcomed. They should be sent to the Alliance for Telecommunications Industry Solutions, Suite 500, 1200 G Street, NW, Washington, DC 20005. This standard was processed and approved for submittal to ANSI by Accredited Standards Committee on Telecommunication T1. Committee a

14、pproval of the standard does not necessarily imply that all committee members voted for its approval. At the time it approved this standard, the T1 Committee had the following members: E.R. Hapeman, T1 Chair W.R. Zeuch, T1 Vice-Chair J.A. Crandall, T1 Director S.M. Carioti, T1 Disciplines S.D. Barcl

15、ay, T1 Secretary C.A. Underkoffler, T1 Chief Editor S. Gorshe, T1 Technical Editor/T1X1 Chief Editor EXCHANGE CARRIERS Organization Represented Name of Representative Ameritech Fred Kujawski Cathy Lazzaro (Alt.) AT k - The number of the information bits; m - The parameter of the BCH code; t - The nu

16、mber of the corrected errors within the block of the BCH code; d - Minimum code distance; and s - The amount of information eliminated as part of the code shortening. 3.3 Generator Polynomial: The polynomial that is used for encoding of any cyclic codes. The remainder after division of the informati

17、on polynomial by the generator polynomial is the redundancy part of the encoded code word. 3.4 optical carrier level N (OC-N): The optical signal that results from an optical conversion of an STS-N signal. SDH does not make the distinction between a logical signal (e.g., STS-N in SONET) and a physic

18、al signal (e.g., OC-N in SONET). The equivalent SDH term for both logical and physical signals is synchronous transport module level M (STM-M), where M=(N/3). There are equivalent STM-M signals only for values of N=3, 12, 48, and 192. 3.5 systematic code: A systematic code is one in which the code b

19、lock is formed by appending the redundant bits to the original data bits without changing the values of the original data bits. In contrast, a non-systematic code is one in which the values of the original data bits are changed when they are mapped into the code block along with the redundant bits.

20、. 4 Abbreviations they are thus appropriate for service-related performance measurements (e.g., as used for protection switching), but give no information about the raw performance of the line. 3. The FEC function “borrows” overhead bytes from the line layer and thus, overwrites bytes currently cove

21、red by B2. The FEC adaptation function shall compensate B2 appropriately. Consequently, the transmitted B2 bytes shall include the FEC check bytes. 4. The transmitted B2 is used to compute FEC check bytes. Hence, B2 bytes are corrected by the FEC. 5. FEC is a line layer function and therefore covers

22、 all the Synchronous Payload Envelope (SPE) plus Line Overhead (LOH) bytes normally processed at the Line Termination Equipment (LTE), but not Section Overhead (SOH) bytes. 6. The FEC layer performance monitoring functions now provide information about the condition of the raw performance of the lin

23、e layer. Use of the in-band FEC performance monitoring information is for further study. 7. Correction is performed on all of the payload envelope capacity and the Line overhead. B2 is used to calculate the corrected Line BER. Raw Line layer BER can be calculated with the aid of FEC correction count

24、s. ATIS-0900105.08.2001 4 6 The FEC Function 6.1 Code Type and Parameters The code is a shortened, systematic binary-BCH code derived from a (8191, 8152) parent code. Sufficient check bits are generated to support triple error correction. The block size is 1 row (bit-slice) of STS-48, i.e., k=4320 i

25、nformation bits plus 39 check bits per block, i.e., n=4359. The minimum code distance=7, i.e., number of correctable errors, t=3. 6.2 FEC Encoder Description and Algorithm The generator polynomial used is G(x) = G1(x)G3(x)G5(x) where: G1(x) = x13+ x4+ x3+ x + 1 G3(x) = x13+ x10+ x9+ x7+ x5+ x4+ 1 G5

26、(x) = x13+ x11+ x8+ x7+ x4+ x + 1 FEC encoding operates on a row-by-row basis. The code word is represented by the polynomial: C(x)= I(x) + R(x) Where: I(x) = a4358x4358+ .+a39x39where the an(n=4358 to 39) represent the information bits; and R(x) = a38x38+ .+a0 where the an(n=38 to 0) represent the

27、check bits. The first bit of the overhead in each code block is the first bit of the code word and is the coefficient a4358of X4358. The information bits not covered (see 6.5 below) in the FEC calculation are replaced with zeros in the FEC encoder and decoder. Since this is a systematic code, the ch

28、eck bits R(x) are provided by: R(x) = I(x) mod G(x) 6.3 Encoder and decoder locations The encoder is always located at the transmitter side of an in-band FEC compliant LTE. There is always a decoder at the input of an in-band FEC compliant LTE. Optionally, a Line Regeneration Equipment (LRE) can dec

29、ode (correct), but shall not re-encode. ATIS-0900105.08.2001 5 6.4 FEC delay characteristic The encode delay shall be no more than 15 s corresponding to one SONET row. The decode delay is no more than 15 s wherever encountered. An LTE compliant with this standard shall have a FEC processing delay of

30、 no more 15 s. In the case of in-band FEC supported in an LRE, each LRE adds no more than 15 s delay. 6.5 SONET and FEC check bits not included in FEC coding. The bits and bytes that are not included in the coding of the FEC are: All SOH bytes including undefined SOH bytes. Note that the FEC Status

31、Indication (FSI) byte(s) are covered by the FEC. All FEC check bits associated with the other code word blocks. Note that although check bits of each code word are not included in I(x), they form the R(x) of the code word C(x) and, as such, can be corrected. 7 Mapping Into the SONET Frame To minimiz

32、e delay relative to maintaining SOH/LOH layer integrity, LOH and SOH for FEC check bits shall be used to keep delay to less than 30 s per encoder/decoder. 7.1 Location of in-band FEC check bits Figures 2 through 10 show the location of FEC check bits for each row. Also, Table 1 shows the location of

33、 the FEC check bits and FSI using the notation used in section 9.2.1 of G.707 and shown in Figure 9-1/G.707 “STM-16 SOH.“ 7.2 Location of status/control bits FEC status/control bits are located in Row 3 (see Table 1). The location of the FSI bits within this row is shown in Figure 12. 7.3 Code block

34、 definition and Interleaving 7.3.1 STS-48 signal The in-band FEC code blocks are designed to cover a single row of the STS-48/STM-16 payload envelope capacity and Line overhead with eight bit-interleaved code blocks that together form a Block Group. Refer to Figure 11 and Figure 13 for a single slic

35、e view and a byte view of the eight bit-interleaved code blocks. The 8 way bit interleaving in conjunction with BCH-3 provides 24 bit burst error correction capability per row. ATIS-0900105.08.2001 6 7.3.2 STS-N signal where N = 192 The code block definition for STS-N signals is identical to that fo

36、r an STS-48 signal. However, there are N/48 Block Groups (i.e., N/48 x 8 code blocks) which are formed by (N/48)-way disinterleaving of the STS-N signal, taking 16 consecutive bytes at a time. 7.4 FEC Status Indication (FSI) The FEC encoder is required to generate the FSI bits to enable downstream d

37、ecoders. This is to prevent downstream decoders from causing errors by miscorrection when FEC encoding is not present. 7.4.1 FSI coding for STS-48 signal The FSI byte is located in Row 3. The FSI bits are bits 7 and 8 of the FSI byte that is the byte immediately preceding the first byte of the 3rd 1

38、3-byte FEC block in Row 3. (See Figure 12). The remaining bits in the FSI bytes are unassigned, but are covered by the FEC. The transmitted default value for these remaining 6 bits shall be zero. The FSI bits (7 and 8) are checked prior to FEC decoding, but the entire FSI byte is included in the FEC

39、 block for correction before retransmission by correcting regenerators. The FSI bit coding is defined in 10.2. 7.4.2 FSI coding for STS-N signal, where N = 192 The FSI byte location is identical for every Block Group. The FSI byte content for the first Block Group transmitted is defined in 10.2. The

40、 FSI byte in the remaining Block Groups are unassigned, but are covered by the FEC. The transmitted default value shall be 00H. 7.5 B1 Calculation at Encoder and Decoder B1 is calculated per T1.105-2001. Note that the FEC check bytes and FSI byte(s) in the SOH are included in the B1 coverage. 7.6 B2

41、 Calculation at Encoder and Decoder B2 is calculated per T1.105-2001. Note that the FEC check bytes and FSI byte(s) in the SOH are not included in the B2 calculation and the FEC check bytes in the LOH are included in the B2 calculation. This ensures backward compatibility of B1 and B2 calculation fo

42、r non-FEC equipment. B2 of the current frame is calculated over the previous frame, including the FEC check bytes. This B2 is included in the FEC check byte calculations of the current frame. The received B2 count is performed after the FEC correction. Errors on the received FEC check byte shall be

43、corrected prior to B2 calculation at the receiver. ATIS-0900105.08.2001 7 8 In-band FEC LRE Functions 8.1 LREs without error correction Equipment that only supports STE functionality shall pass through FEC check bits plus the FSI byte(s) unaltered. 8.2 LRE with error correction Optionally equipment

44、that only supports STE functionality can perform FEC decoding and correction without re-encoding. The corrected FEC check bits plus FSI byte(s) are forwarded. 9 Performance Monitoring 9.1 FEC Correctable Error Count Correctable errors are those that are detected and corrected. Raw Line layer BER can

45、 be calculated with the aid of FEC correction counts. If LRE error correction is performed, then the FEC correctable error count reflects the raw BER from the last decoding point. 9.2 FEC Uncorrectable Error Count Uncorrectable errors are those that are detected but not corrected. The use of this is

46、 for further study. 9.3 Error Count after FEC decoding B2 is used to calculate the error count after the FEC decoding at the LTE. 10 FEC Activation and Deactivation 10.1 FEC Operational States 10.1.1 Encoder States There are three operational states: 1) FEC on; 2) FEC off with encoder delay; and 3)

47、FEC off without encoder delay. The encoder operational state is controlled by the management layer. Transitions to/from state 3 affect data path delay and will not be hitless. ATIS-0900105.08.2001 8 10.1.2 Decoder States. There are three operational states: 1) FEC correction enabled; 2) FEC correcti

48、on off with decoder delay; and 3) FEC correction off without decoder delay. The state transitions to/from state 3 is solely under management layer control and affects data path delay. Therefore, this transition is not hitless. State transitions between state 1 and 2 are controlled by the received FS

49、I. 10.2 FEC Status Indication (FSI) 10.2.1 FSI Interaction with Decoder States Decoder State 1 can only be entered with received FSI “on” condition. If operating in decoder State 1 and FSI “off” is received then the decoder shall enter State 2. The transitions between State 1 and State 2 shall occur in a hitless manner. 10.2.2 FEC On/Off State Indication Generation at Transmitter When the encoder is in State 1, FSI = 01 is transmitted. When the encoder is in State 2 or State 3, FSI = 00. FSI = 10 and 11 are not valid encoder transmission values. In order to permit synch