JEDEC JEP163-2015 Selection of Burn-In Life Test Conditions and Critical Parameters for QML Microcircuits.pdf
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1、JEDEC PUBLICATION Selection of Burn-In/Life Test Conditions and Critical Parameters for QML Microcircuits JEP163 SEPTEMBER 2015 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of
2、Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and a
3、ssisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption m
4、ay involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents
5、 a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in c
6、onformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Docume
7、nts for alternative contact information. Published by JEDEC Solid State Technology Association 2015 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the indiv
8、idual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Ass
9、ociation 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 163 -i- SELECTION OF BURN-IN/LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML MICROCIRCUITS Contents PageForeword iiIntroducti
10、on ii1 Scope 12 References 13 Terms and definitions 24 Wafer Fabrication and Design Considerations 45 Burn-in Stress and Electrical Test Conditions Development 56 Life Test Stress and Electrical Test Conditions Development 10Annex A (informative) Example Burn-in Condition Evaluations 14Annex B (norm
11、ative)Burn-in and Electrical Measurement Requirements 19JEDEC Publication No. 163 -ii- Foreword This publication was developed as a guideline to assist manufacturers of integrated circuits (microcircuits) in defining the conditions for burn-in and life test of their products to meet the quality and
12、reliability performance requirements of MIL-PRF-38535 and the applicable Standard Military Drawing. Documentation of the manufacturers technical rationale in accordance with this guideline will also facilitate customer understanding and acceptance of the manufacturers Quality Management (QM) plan. I
13、ntroduction MIL-PRF-38535, in conjunction with MIL-STD-883, defines the basic screening requirements for compliant microcircuits. MIL-STD-883 Test Method 5004 specifies two independent burn-in conditions for Class Level S devices. A dynamic burn-in is performed for 240 hours at 125 C. A static or re
14、verse bias burn-in is performed for 72 hours at 150 C. Per Test Method 5004 the reverse bias burn-in is a requirement only when specified in the applicable device specification (i.e. Standard Military Drawing) and is recommended only for a certain MOS, linear or other microcircuits where surface sen
15、sitivity may be of concern. These requirements have been part of the military standards for decades and originated at a time when design rules and wafer fabrication processes were much less advanced than current state-of-the art technologies. With the advent of improved wafer fabrication processes,
16、Statistical Process Controls (SPC), Wafer Level Reliability (WLR), Circuit Design Tools, Design-For-Test (DFT) techniques, and modern simulation and characterization techniques, the presence of certain failure modes have been reduced and/or eliminated for certain wafer fabrication processes. However
17、, deep submicron and System On A Chip wafer fabrication processes have potentially greater transistor to transistor process variations; hence, they may have a greater need for burn-in and life test to evaluate and screen infant life mortality. Due to the current variation in geometry sizes and diffe
18、rent levels of technology maturity and circuit designs, the establishment of the appropriate burn-in/life test stress and test conditions must be evaluated in relation to each products wafer fabrication process and circuit design techniques. The stress conditions must demonstrate adequate Early Fail
19、ure detection and Intrinsic Failure Rate (IFR) performance that meets customer failure rate requirements. For example, a typical space application has a goal of 10 to 15 years operating life. JEDEC Publication No. 163 Page 1 SELECTION OF BURN-IN/LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML M
20、ICROCIRCUITS (From JEDEC Board Ballot JCB-15-29, formulated under the cognizance of the JC-13.2 Government Liaison Committee on Microelectronic Devices) 1 Scope This publication is intended as a guideline to develop and establish conditions for burn-in and life test of MIL-PRF-38535 QML integrated c
21、ircuits. These guidelines are intended to provide manufacturers with a consistent means of defining burn-in and life test stress and electrical test requirements acceptable to user organizations and for the development of Standard Military Drawings. The guidelines cover the entire design, wafer fabr
22、ication and manufacturing flows, including design and process awareness. Without design awareness (critical circuit blocks / functionality, etc.), burn-in / life test of an integrated circuit might be compromised, or it might dramatically shorten the devices life prior to system use. 2 References EE
23、E-INST-002, Instructions for EEE Parts Selection, Screening, Qualification, and Derating (NASA Goddard Space Flight Center) JEP122, Failure Mechanisms and Models for Semiconductor Devices JESD85, Methods for Calculating Failure Rates in Units of FITs MIL-HDBK-1331, Handbook for Parameters to be Cont
24、rolled for the Specification of Microcircuits (DLA Land and Maritime) MIL-PRF-38535, General Specification for Integrated Circuits (Microcircuits) Manufacturing (DLA Land and Maritime) MIL-STD-883, Test Method Standard Microcircuits (DLA Land and Maritime) JEDEC Publication No. 163 Page 2 3 Terms an
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