DLA DSCC-VID-V62 12628-2012 MICROCIRCUIT LINEAR 2 5 V TO 5 5 V 500 礎 QUAD VOLTAGE OUTPUT 12 BIT DAC IN 10-LEAD PACKAGE MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original date

2、 of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, LINEAR, 2.5 V TO 5.5 V, 500 A, QUAD VOLTAGE OUTPUT 12 BIT DAC IN 10-LEAD PACKAGE, MONOLITHIC SILICON 12-10-26 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12628 REV PAGE 1 OF 10 AMSC N/A 5962-V020-13 Provided by

3、 IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12628 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 2.5 V to 5.5 V, 500 A, quad v

4、oltage output 12 bit DAC in 10 lead package microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identif

5、ying the item on the engineering documentation: V62/12628 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 AD5324-EP 2.5 V to 5.5 V, 500 A, quad voltage output 12 bit DAC in 10 lead package

6、1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 10 JEDEC MO-187-BA Mini Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Fini

7、sh designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12628 REV PA

8、GE 3 1.3 Absolute maximum ratings. 1/ 2/ VDDto GND . -0.3 V to +7.0 V Digital input voltage to GND -0.3 V to VDD+ 0.3 V Reference input voltage to GND . -0.3 V to VDD+ 0.3 V VOUTA through VOUTD to GND . -0.3 V to VDD+ 0.3 V Operating temperature range: Industrial -55C to +125C Storage temperature ra

9、nge -65C to 150C Junction temperature (TJmax) . 150C Case outline X Power dissipation . (TJ max TA)/ JAJAThermal impedance 206C/W JCThermal impedance . 44C/W Reflow soldering Peak temperature 220C Time at peak temperature 10 sec to 40 sec 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIAT

10、ION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be

11、permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with

12、items A and C (if applicable) above. 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating c

13、onditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ Transient currents of up to 100 mA do not cause SCR latch up. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND

14、 MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12628 REV PAGE 4 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3 and table I herein. 3.4 Design, construction, and physical dimension.

15、The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function sh

16、all be as shown in figure 3. 3.5.4 Functional block diagram. The functional block diagram shall be as shown in figure 4. 3.5.5 Serial Interface timing diagram. The serial Interface timing diagram shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted with

17、out license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12628 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions 2/ Limits Unit Min Max DC Performance 3/ Resolution 12 TYP Bits Relative accuracy 10 LSB Differential

18、 nonlinearity 4/ 5/ 1 LSB Offset error See FIGURE 5 3 % of FSR Gain error See FIGURE 5 1 % of FSR Lower dead band 6/ 60 mV Offset error drift 7/ -12 TYP ppm of FSR/C Gain error drift 7/ -5 TYP ppm of FSR/C DC power supply rejection ratio 7/ VDD= %10 -60 TYP dB DC crosstalk 7/ RL= 2 k to GND or VDD20

19、0 TYP V DAC reference inputs 7/ VREFinput range 0.25 VDDV VREFinput impedance Normal operation 37 k Power down mode 10 TYP M Reference feedthrough Frequency = 10 kHz -90 TYP dB Output characteristics 7/ Minimum output voltage 8/ 9/ 0.001 TYP V Maximum output voltage 8/ 10/ VDD 0.001 TYP DC output im

20、pedance 0.5 TYP Short circuit current VDD= 5 V 25 TYP mA VDD= 3 V 16 TYP Power up time Coming out of power down mode VDD= 5 V 2.5 TYP s Coming out of power down mode VDD= 3 V 5 TYP Logic inputs 7/ Input current 1 A Input low voltage VILVDD= 5 V 10% 0.8 V VDD= 3 V 10% 0.6 VDD= 2.5 V 0.5 Input high vo

21、ltage VIHVDD= 5 V 10% 2.4 VDD= 3 V 10% 2.1 VDD= 2.5 V 2.0 Pin capacitance 3 TYP pF Power requirements VDD2.5 5.5 V IDD(Normal mode) 11/ VDD= 4.5 V to 5.5 V VDD= 2.5 V to 3.6 V VIH= VDDand VIL= GND 900 A VIH= VDDand VIL= GND 700 A IDD(Power down mode) VDD= 4.5 V to 5.5 V VDD= 2.5 V to 3.6 V VIH= VDDa

22、nd VIL= GND 1 A VIH= VDDand VIL= GND 1 A See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12628 REV PAGE 6 TABLE I. Electrical performance chara

23、cteristics - Continued. 1/ Test Symbol Test conditions 2/ Limits Unit Min Max AC characteristics Output voltage settling time VREF= VDD= 5 V; scale to scale change (0x400 to 0xC00) 10 s Slew rate 0.7 TYP V/s Major code transition glitch energy 1 LSB change around major carry 12 TYP nV-sec Digital fe

24、edthrough 1 TYP Digital crosstalk 1 TYP DAC to DAC crosstalk 3 TYP Multiplying bandwidth VREF= 2 V 0.1 Vp-p200 TYP kHz Total harmonic distortion VREF= 2.5 V 0.1 Vp-p, frequency = 10 kHz -70 TYP dB Test Symbol Test conditions 2/ 2.5 V VDD 3.6 V 3.6 V VDD 5.5 V Unit Min Max Min Max Timing characterist

25、ics 7/ 12/ (see FIGURE 5) SCLK cycle time t140 33 ns SCLK high time t216 13 SCLK low time t316 13 SYNCto SCLK falling edge setup time t4 16 13 Data setup time t55 5 Data hold time t64.5 4.5 SCLK falling edge to SYNCrising edge t7 0 0 Minimum SYNChigh time t8 80 33 1/ Testing and other quality contro

26、l techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product pe

27、rformance is assured by characterization and/or design. 2/ VDD= 2.5 V to 5.5 V; VREF= 2 V; RL= 2 k to GND; CL= 200 pF to GND; TA= -55C to +125C; TA= 25C for typical (TYP) value; unless otherwise noted. 3/ DC specifications tested with the output unloaded. 4/ Linearity is tested using a reduced code

28、range: Code 115 to Code 3981. 5/ Guaranteed monotonic by design over all code. 6/ Lower dead band exits only if offset error is negative. 7/ Guaranteed by design and characterization, not production test. 8/ For the amplifier output to reach its minimum voltage, offset error must be negative. For th

29、e amplifier output to reach its maximum voltage, VREF= VDDand offsets plus gain error must be positive. 9/ Measurement of the minimum and maximum. 10/ V drive capability of the output amplifier. 11/ IDDspecification is valid for all DAC codes; interface inactive; load currents excluded. 12/ All inpu

30、t signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL+ VIH)/2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12628 REV PAG

31、E 7 Case X eb10 PLSE E1D10ASEATINGPLANEc6PIN 1INDEX AREAA2A10-6L5Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max A 1.10 D/E 2.90 3.10 A1 0.05 0.15 E1 4.65 5.15 A2 0.75 0.95 e 0.50 BSC b 0.17 0.33 L 0.40 0.80 c 080 0.23 NOTES: 1. All linear dimensions are in millimeters. 2. Falls wit

32、hin JEDEC MO-15-AB3. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12628 REV PAGE 8 Case outline X Terminal number Terminal symbol Terminal number

33、Terminal symbol 1 VDD10 SYNC2 VOUTA 9 SCLK 3 VOUTB 8 DIN 4 VOUTC 7 GND 5 REFIN 6 VOUTD FIGURE 2. Terminal connections. Terminal Description Number Mnemonic 1 VDDPower supply input. This part can be operated from 2.5 V to 5.5 V and the supply can be decoupled to GND 2 VOUTA Buffered analog output vol

34、tage from DAC A. The output amplifier has rail to rail operation. 3 VOUTB Buffered analog output voltage from DAC B. The output amplifier has rail to rail operation. 4 VOUTC Buffered analog output voltage from DAC C. The output amplifier has rail to rail operation. 5 REFIN Reference input pin for al

35、l four DACs. It is an input range from 0.25 V to VDD. 6 VOUTD Buffered analog output voltage from DAC D. The output amplifier has rail to rail operation. 7 GND Ground reference point for all circuitry on the part. 8 DIN Serial data input. This device has a 16 bit shift register on the falling edge o

36、f the serial clock input. Data can be transferred at clock speeds up to 30 MHz. The SCLK input buffer is powered down after each writer cycle. 9 SCLK Serial clock input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at clock spee

37、ds up to 30 MHz. The SCLK input buffer is powered down after each write cycle. 10 SYNCActive low control input. This is the frame synchronization signal for the input data. When SYNCgoes low, it enables the input shift register and data is transferred in on the falling edge of the foolowing 16 clock

38、s. If SYNCis taken high before 16thfalling edge of SCLK. the rising edge of SYNCacts as an interrupt and the write sequence is ignored by the device. FIGURE 3. Terminal function. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME C

39、OLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12628 REV PAGE 9 INPUTREGISTERDACREGISTERSTRINGDAC AINPUTREGISTERDACREGISTERSTRINGDAC BINPUTREGISTERDACREGISTERSTRINGDAC CINPUTREGISTERDACREGISTERSTRINGDAC DBUFFERBUFFERBUFFERBUFFERPOWER-DOWN LOGICPOWER-ON RESETINTERFACELOGICGNDSCLKDINSYNCLDACVDD

40、 REFINVOUTAVOUTBVOUTCVOUTDFIGURE 4. Functional block diagram. SCLKSYNCDIN DB15 D05t8t4t3t2t7t1t5t6FIGURE 5. Serial interface timing diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16

41、236 DWG NO. V62/12628 REV PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, c

42、lassification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6.

43、 NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes wi

44、thout notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime main

45、tains an online database of all current sources of supply at http:/www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/12628-01XE 24355 AD5324SRMZ-EP-RL7 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 24355 Analog Devices 1 Technology Way P.O. Box 9106 Norwood, MA 02062-9106 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-