DLA DSCC-VID-V62 03604 REV A-2009 MICROCIRCUIT DIGITAL ADVANCED HIGH SPEED CMOS QUADRUPLE 2-INPUT POSITIVE NAND GATE MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 09-02-17 Charles F. Saffle Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV A A A A A A A A A A A REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARE

2、D BY Thanh V. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Thanh V. Nguyen APPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, ADVANCED HIGH SPEED CMOS, QUADRUPLE 2-INPUT POSITIVE NAND GATE, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 D

3、WG NO. V62/03604 YY-MM-DD 02-11-07 REV A PAGE 1 OF 11 AMSC N/A 5962-V037-09 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03604 REV A PAGE 2 1. SCOPE 1.1 Scope.

4、 This drawing documents the general requirements of a high performance quadruple 2-input positive NAND gate microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item

5、drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03604 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 74AHC00-EP Quadrupl

6、e 2-input positive NAND gate 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 MS-012 Plastic small-outline package Y 14 MO-153 Plastic small-outline package 1.2.3 Lead finishes. The lead finishes are as specified below or

7、 other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, C

8、OLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03604 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 7.0 V Input voltage range (VI). -0.5 V to 7.0 V 2/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ Input clamp current (IIK) (VI 0) . -20 mA O

9、utput clamp current (IOK) (VO 0 or VO VCC) . 20 mA Continuous output current (IO) (VO= 0 to VCC) 25 mA Continuous current through VCCor GND. 50 mA Storage temperature range (TSTG). -65C to 150C Package thermal impedance (JA): 3/ X package .86C/W Y package .113C/W 1.4 Recommended operating conditions

10、. 4/ 5/ Supply voltage range (VCC) . 2.0 V to 5.5 V Input voltage range (VI). 0.0 V to 5.5 V Output voltage range (VO) . 0.0 V to VCCMinimum high level input voltage (VIH): VCC= 2.0 V 1.5 V VCC= 3.0 V 2.1 V VCC= 5.5 V 3.85 V Maximum low level input voltage (VIL): VCC= 2.0 V 0.5 V VCC= 3.0 V 0.9 V VC

11、C= 5.5 V 1.65 V Maximum high level output current (IOH): VCC= 2.0 V -50 A VCC= 3.3 V 0.3 V -4.0 mA VCC= 5.0 V 0.5 V -8.0 mA Maximum low level output current (IOL): VCC= 2.0 V 50 A VCC= 3.3 V 0.3 V 4.0 mA VCC= 5.0 V 0.5 V 8.0 mA Maximum input transition rise or fall rate (t/V): VCC= 3.3 V 0.3 V 100 n

12、s/V VCC= 5.0 V 0.5 V 20 ns/V Operating free-air temperature range (TA). -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyon

13、d those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The package th

14、ermal impedance is calculated in accordance with JESD 51-7. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 5/ All unuse

15、d inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03604 REV A PAGE 4 2. APPLICABL

16、E DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington

17、, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 U

18、nit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I her

19、ein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3

20、Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproducti

21、on or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03604 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Limits Test Symbol Conditions VCC Temperature, TA Device type Min Max Unit 2.0 V 1.9 3

22、.0 V 2.9 IOH= -50 A 4.5 V 25C, -55C to 125C 4.4 25C 2.58 IOH = -4 mA 3.0 V -55C to 125C 2.48 25C 3.94 High level output voltage VOH IOH= -8 mA 4.5 V -55C to 125C All 3.80 V 2.0 V 0.1 3.0 V 0.1 IOL= 50 A 4.5 V 25C, -55C to 125C 0.1 25C 0.36 IOL = 4 mA 3.0 V -55C to 125C 0.5 25C 0.36 Low level output

23、voltage VOL IOL= 8 mA 4.5 V -55C to 125C All 0.5 V 25C All 0.1 Input current II VI = 5.5 V or GND 0.0 V to 5.5 V -55C to 125C 1.0 A 25C All 2.0 Quiescent supply current ICC VI= VCCor GND IO= 0 A 5.5 V -55C to 125C 20.0 A Quiet output, maximum dynamic VOL VOL(P)2/ 5.0 V 25C All 0.8 V Quiet output, mi

24、nimum dynamic VOL VOL(V)2/5.0 V 25C All -0.8 V Quiet output, minimum dynamic VOH VOH(V)2/5.0 V 25C All 4.6 typical V High level dynamic input voltage VIH(D)2/5.0 V 25C All 3.5 V Low level dynamic input voltage VIL(D)2/CL= 50 pF 5.0 V 25C All 1.5 V See footnote at end of table. Provided by IHSNot for

25、 ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03604 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Limits Test Symbol Conditions VCC Temperature, TA Devi

26、ce type Min Max Unit Input capacitance CI VI= VCCor GND 5.0 V 25C All 10 pF Power dissipation capacitance CPD No load f = 1 MHz 5.0 V 25C All 9.5 typical pF 25C 7.9 3.0 V and 3.6 V -55C to 125C 1.0 9.5 25C 5.5 CL= 15 pF See figure 5 4.5 V and 5.5 V -55C to 125C All 1.0 6.5 25C 11.4 3.0 V and 3.6 V -

27、55C to 125C 1.0 13.0 25C 7.5 Propagation delay time, A or B to Y tPLH, tPHL CL= 50 pF See figure 5 4.5 V and 5.5 V -55C to 125C All 1.0 8.5 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. P

28、roduct may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Characteristics are for surface-mount packages only. Provided b

29、y IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03604 REV A PAGE 7 Case X Dimensions Inches Millimeters Inches Millimeters Symbol Min Max Min Max Symbol Min Max Min Max A .0

30、69 1.75 E .150 .157 3.81 4.00 A1 .004 .010 0.10 0.25 E1 .228 .244 5.80 6.20 b .014 .020 0.35 0.51 e .050 BSC 1.27 BSC c .008 NOM 0.20 NOM L .016 .044 0.40 1.12 D .337 .344 8.55 8.75 NOTES: 1. All linear dimensions are in inches (millimeters). 2. This case outline is subject to change without notice.

31、 3. Body dimensions do not include mold flash or protrusion, not to exceed .006 inches. 4. Fall within JEDEC MS-012. FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE I

32、DENT NO. 16236 DWG NO. V62/03604 REV A PAGE 8 Case Y Dimensions Inches Millimeters Inches Millimeters Symbol Min Max Min Max Symbol Min Max Min Max A .047 1.20 E .169 .177 4.30 4.50 A1 .002 .006 0.05 0.15 E1 .244 .260 6.20 6.60 b .007 .012 0.19 0.30 e .026 BSC 0.65 BSC c .006 NOM 0.15 NOM L .020 .03

33、0 0.50 0.75 D .193 .201 4.90 5.10 NOTES: 1. All linear dimensions are in millimeters (inches). 2. This case outline is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 millimeters. 4. Fall within JEDEC MO-153. FIGURE 1. Case outlines -

34、Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03604 REV A PAGE 9 Inputs Output A B Y H H L L X H X L H H = High voltage level L = Low voltage level X

35、= Dont care FIGURE 2. Truth table. FIGURE 3. Logic diagram. Device type 01 Case outlines: X and Y Terminal number Terminal symbol Terminal number Terminal symbol 1 1A 8 3Y 2 1B 9 3A 3 1Y 10 3B 4 2A 11 4Y 5 2B 12 4A 6 2Y 13 4B 7 GND 14 VCC FIGURE 4. Terminal connections. Provided by IHSNot for Resale

36、No reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03604 REV A PAGE 10 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output

37、 is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50 , tr 3 ns, tf 3 ns.

38、 4. The outputs are measured one at a time with one input transition per measurement. FIGURE 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16

39、236 DWG NO. V62/03604 REV A PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,

40、 classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices.

41、6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes

42、without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing admi

43、nistrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/03604-01XE 01295 SN74AHC00MDREP AHC00MEP V62/03604-01YE 01295 SN74AHC00MPWREP HA00MEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering

44、 documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-