JEDEC JESD65B-2003 Definition of Skew Specifications for Standard Logic Devices《标准逻辑设备的歪斜规范定义》.pdf
《JEDEC JESD65B-2003 Definition of Skew Specifications for Standard Logic Devices《标准逻辑设备的歪斜规范定义》.pdf》由会员分享,可在线阅读,更多相关《JEDEC JESD65B-2003 Definition of Skew Specifications for Standard Logic Devices《标准逻辑设备的歪斜规范定义》.pdf(19页珍藏版)》请在麦多课文档分享上搜索。
1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD65BSEPTEMBER 2003JEDECSTANDARDDefinition of Skew Specificationsfor Standard Logic Devices(Revision of JESD65-A)NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Council level and subsequ
2、ently reviewed and approved by the EIA General Counsel.JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchaser in sele
3、cting and obtaining with minimum delay theproper product for use by those other than JEDEC members, whether the standard is to be used eitherdomestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoption mayinvolve patents or articles, ma
4、terials, or processes. By such action JEDEC does not assume any liability toany patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards orpublications.The information included in JEDEC standards and publications represents a sound approach to productspecifica
5、tion and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication
6、 shouldbe addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA22201-3834, (703)907-7559 or www.jedec.org.Published byJEDEC Solid State Technology Association 20032500 Wilson BoulevardArlington, VA 22201-3834This documentmay be downloaded free of charge, however
7、 JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material.Price: Please refer to the current Catalog of JEDEC Engineering Standards and Publicationsat www.jedec.org or cal 703.907.7759Printed in the U.S.A.All righ
8、ts reservedPLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology A
9、ssociation 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 65BPage 1DEFINITIONS OF SKEW SPECIFICATIONS FOR STANDARD LOGIC DEVICES(From JEDEC Board Ballots JCB-02-67, JCB-02-112, JCB-02-113, and JCB-02-114, formulated under the cognizance of the JC-40 Co
10、mmittee on Digital Logic.)1 ScopeThis standard defines skew specifications and skew testing for standard logic devices.The purpose is to provide a standard for specifications to achieve uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by user
11、s.2 Terms and definitions These definitions are provided for the purpose of this document. For general definitions of skew time, see the latest revision of JEDEC Standard No. 99 Terms, Definitions, and Letter Symbols for Microelectronic Devices.2.1 Device terms and definitionsPLL device: A logic dev
12、ice that includes a phase-locked loop and may also include other logic functions, such as counters, registers, and buffers.2.2 Parameter terms and definitionsskew (time): The magnitude of the time difference between two events that ideally would occur simultaneously. controlled edge: The output sign
13、al edge that is locked to the PLL trigger reference. jitter: The time deviation of a PLL-generated controlled edge from its nominal position.threshold crossing: The point at which a logic signal transitions from one logic state to another.primary threshold crossing: The threshold crossing of a clock
14、 signal indicating the start of a new cycle and the end of the previous cycle.secondary threshold crossing: The threshold crossing of a clock signal indicating the second part of the clock cycle. JEDEC Standard No. 65BPage 23 Standard specificationsAll skew parameters are specified over the guarante
15、ed temperature and supply operating ranges. If more than one temperature or supply operating range is used, the range(s) for the skew specification(s) must be identified. PLL logic devices must be supplied with a stable input reference clock within the operating frequency range of the component.Tabl
16、e 1 Symbols for skew and other specifications NOTE 1 This parameter is not production tested. NOTE 2 The sample size shall be greater than or equal to 1000.NOTE 3 The sample size shall be greater than or equal to 2000.NOTE 4 The test load for this parameter may be a nonstandard load identified in th
17、e data sheet.Table 2 Example of suggested jitter specificationsNOTE 5 Test Loads and Conditions are shown in Clause 4 “Standard test circuits for skew testing” for the designated voltage range.NOTE 6 Operating frequency range is 10 MHz to 100 MHz.Symbol Parameter Units Notestsk(o)output skew ps, ns
18、1tsk(LH)output skew for low-to-high transitions ps, nstsk(HL)output skew for high-to-low transitions ps, nstsk(pr)process skew ps, nstsk(pp)part-to-part skew ps, nstsk(b)bank skew ps, ns 1tsk(p)pulse skew ps, nstsk(inv)inverting skew ps, ns 1, 4tsk()multiple-frequency skew ps, nst()static phase offs
19、et ps, nst()dyndynamic phase offset ps, nst()tottotal phase offset ps, nstjit(cc)cycle-to-cycle period jitter ps, ns 2, 5 tjit(per)period jitter ps, ns 2, 5tjit(hper)half-period jitter ps, nstjit(duty)duty cycle jitter ps, nstjit()phase jitter ps, ns 1, 3, 5lock (f) frequency lockedlock ()phase lock
20、edtLpower-up PLL lock time ns, mstL()PLL lock time after frequency change ns, mstrecL()PLL recovery after phase change ns, msnLcycles to acquire PLL lock cyclesODC PLL output duty cycle %Symbol Parameter Sample size Typ Max Unit Notestjit(cc)cycle-to-cycle period jitter 1,000 cycles x x ps 5, 6tjit(
21、per)period jitter 10,000 cycles x x ps 5, 6tjit()phase jitter 2,000 cycles x x ps 5, 6JEDEC Standard No. 65BPage 33 Standard specifications (contd)output skew (tsk(o): The skew between specified outputs of a single logic device with all driving inputs switching simultaneously and the outputs driving
22、 identical specified loads.An example of a multiple bank logic deviceAn example of a logic device without banksAn example of output waveformsOUTPUT 1INPUTOUTPUT 2OUTPUT 3OUTPUT 4OUTPUT 1INPUTOUTPUT 2OUTPUT 3OUTPUT 4INPUTOUTPUT 3OUTPUT 1tsk(o)tsk(o)VOHVOLVrefVOHVOLVrefVtest0 VVrefJEDEC Standard No. 6
23、5BPage 43 Standard specifications (contd)output skew (tsk(LH), tsk(HL): The skew between specified outputs of a single logic device when the outputs have identical specified loads and are switching in the same direction. NOTE Each input-to-output delay time is tested individually, and the difference
24、 is the skew.An example of a multiple bank logic deviceAn example of a logic device without banksAn example of output waveformsOUTPUT 1INPUT 1OUTPUT 2OUTPUT 3OUTPUT 4INPUT 3INPUT 2INPUT 4INPUTOUTPUT 3OUTPUT 1VOHVOLVrefVOHVOLVrefVtest0 VVreftsk(LH)=-tPLH(1)tPLH(3)tPHL(3)tPHL(1)tPLH(1) tPLH(3)tsk(HL)=
- 1.请仔细阅读文档,确保文档完整性,对于不预览、不比对内容而直接下载带来的问题本站不予受理。
- 2.下载的文档,不会出现我们的网址水印。
- 3、该文档所得收入(下载+内容+预览)归上传者、原创作者;如果您是本文档原作者,请点此认领!既往收益都归您。
下载文档到电脑,查找使用更方便
10000 积分 0人已下载
下载 | 加入VIP,交流精品资源 |
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- JEDECJESD65B2003DEFINITIONOFSKEWSPECIFICATIONSFORSTANDARDLOGICDEVICES 标准 逻辑 设备 歪斜 规范 定义 PDF

链接地址:http://www.mydoc123.com/p-807242.html