ETSI ETS 300 462-2-1996 Transmission and Multiplexing (TM) Generic Requirements for Synchronization Networks Part 2 Synchronization Network Architecture《传输和复用 (TM) 同步网络的通用要求 第2部分 同_1.pdf

《ETSI ETS 300 462-2-1996 Transmission and Multiplexing (TM) Generic Requirements for Synchronization Networks Part 2 Synchronization Network Architecture《传输和复用 (TM) 同步网络的通用要求 第2部分 同_1.pdf》由会员分享，可在线阅读，更多相关《ETSI ETS 300 462-2-1996 Transmission and Multiplexing (TM) Generic Requirements for Synchronization Networks Part 2 Synchronization Network Architecture《传输和复用 (TM) 同步网络的通用要求 第2部分 同_1.pdf（19页珍藏版）》请在麦多课文档分享上搜索。

1、W 3400855 0332890 79b ETSI ETC 300 462-2 September 1996 Source: ETSI TC-TM Reference: DE/TM-03017-2 ICs: 33.080 Key words: synchronization, timing, transmission Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 2: Synchronization network architecture ETSI Eu

2、ropean Telecommunications Standards Institute ETSI Secretariat Postal address: F-O6921 Sophia Antipolis CEDEX - FRANCE Office address: 650 Route des Lucioles - Sophia Antipolis - Valbonne - FRANCE X.400: c=fr, a=atlas, p=etsi, s=secretariat - Internet: secretariatetsi.fr Tel.: +33 92 94 42 O0 - Fax:

3、 +33 93 65 47 16 Copyright Notification: No part may be reproduced except as authorized by written permission. The copyright and the foregoing restriction extend to reproduction in all media. Q European Telecommunications Standards Institute 1996. All rights reserved. ETSI ETS*300*462- 2 96 3400855

4、Ol13289L 622 Page 2 ETS 300 462-2: September 1996 _ Whilst every care has been taken in the preparation and publication of this document, errors in content, typographical or otherwise, may occur. if you have comments concerning its accuracy, please write to “ETSI Editing and Committee Support Dept.“

5、 at the address shown on the title page. ETSI ETSs300mYb2- 2 7b m 3Y00855 0132892 569 = Page 3 ETS 300 462-2: September 1996 Contents Foreword . 5 1 2 3 4 5 6 7 8 9 10 11 Scope 7 Normative references 7 Definitions and abbreviations 8 3.1 Definitions 8 3.2 Abbreviations . 8 Synchronization methods 8

6、4.1 Master-slave synchronization 8 4.2 Mutual synchronization 9 Functional description of clock types . 9 Primary Reference Clock (PRC) . 9 Synchronization Supply Unit (SSU) . 9 SDH Equipment Clock (SEC) 10 Synchronization network architecture . 11 Synchronization modes . 13 Synchronization network

7、reference chain . 14 Synchronization strategy . 16 Synchronization network evolution 16 Synchronization network robustness . 16 5.1 5.2 5.3 Annex A (informative): Bibliography 18 History 19 Page 4 ETS 300 462-2: September 1996 ETSI ETS*300*4b2- 2 9b W 3400855 0132893 iT5 m Blank page ETSI ETS*300*46

8、2- 2 9b W 3400855 0332894 333 W Pane 5 ETS 300 462-2: September f996 Foreword This European Telecommunication Standard (ETS) has been produced by the Transmission and Multiplexing (TM) Technical Committee of the European Telecommunications Standard Institute (ETSI). This ETS provides requirements fo

9、r synchronization networks that are compatible with the performance requirements of digital networks. This ETS consists of 6 parts as follows: Part 1: “Definitions and terminology for synchronization networks“ (ETS 300 462-1). Part 2: “Synchronization network architecture“. Pari 3: “The control of j

10、itter and wander within synchronization networks“ (ETS 300 462-3). Pari 4: “Timing characteristics of slave clocks suitable for synchronization supply to Synchronous Digital Hierarchy (SDH) and Plesiochronous Digital Hierarchy (PDH) equipment“ (ETS 300 462-4). Part 5: “Timing characteristics of slav

11、e clocks suitable for operation in Synchronous Digital Hierarchy (SDH) equipment“ (ETS 300 462-5). Part 6: “Timing characteristics of primary reference clocks“ (ETS 300 462-6). NOTE: Parts 4, and 6 of this ETS are being developed by STC TM 3 and are not yet available. Transposition dates Date of ado

12、ption of this ETS: Date of latest announcement of this ETS (doa): 16 August 1996 31 December 1996 Date of latest publication of new National Standard or endorsement of this ETS (dop/e): 30 June 1997 Date of withdrawal of any conflicting National Standard (dow): 30 June 1997 ETSI ETS*300*462- 2 96 34

13、00855 0132895 278 Page 6 ETS 300 462-2: September 1996 Blank page ETSI ETS%300*462- 2 7b E 3400855 013289b I104 Page 7 ETS 300 462-2: September 1996 1 Scope This European Telecommunication Standard (ETS) specifies the architectural principles that should be applied for the design of synchronization

14、networks that are suitable for the synchronization of Synchronous Digital Hierarchy (SDH) and Plesiochronous Digital Hierarchy (PDH) networks. It supports the construction of synchronization networks that support both the short term stability requirements of SDH networks and the long term stability

15、requirements of PDH networks. It applies to the design of new synchronization networks. It does not characterize existing PDH synchronization networks. 2 Normative references This ETS incorporates by dated and undated reference, provisions from other publications. These normative references are cite

16、d at the appropriate places in the text and the publications are listed hereafter. For dated references, subsequent amendments to or revisions of any of these publications apply to this ETS only when incorporated in it by amendment or revision. For undated references the latest edition of the public

17、ation referred to applies. 51 prETS 300 462-1 (1 996): “Transmiscion and Multiplexing (TM); Generic requirements for synchronization networks; Part 1 : Definitions and terminology for synchronization networks“. prETS 300 462-3 (1 996): “Transmission and Multiplexing (TM); Generic requirements for sy

18、nchronization networks; Part 3: The control of jitter and wander within synchronization networks“. ETS 300 147 (1 995): “Transmiscion and Multiplexing (TM); Synchronous Digital Hierarchy (SDH) Multiplexing structure“. ETS 300 462-5 (1 996): “Transmission and Multiplexing (TM); Generic requirements f

19、or synchronization networks; Part 5: Timing characteristics of slave clocks suitable for operation in Synchronous Digital Hierarchy (SDH) equipment“. ETS 300 462-6: “Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 6: Timing characteristics of primary refer

20、ence clocks“. ETSI ETS*LZ- z 96 9 3400855 onwu 040 m Page 8 ETS 300 462-2: September 1996 3 Definitions and abbreviations 3.1 Definitions For the purposes of this ETS, the definitions given in ETS 300 462-1 i apply. 3.2 Abbreviations For the purposes of this ETS, the following abbreviations apply: A

21、IS NE PDH PPm PRC PSTN SASE SDH SEC SETS ssu STM-N TU Alarm Indication Signal Network Element Plesiochronous Digital Hierarchy parts per million Primary Reference Clock Public Switched Telephone Network Stand-Alone Synchronization Equipment Synchronous Digital Hierarchy SDH Equipment Clock SDH Equip

22、ment Timing Source Synchronization Supply Unit Synchronous Transport Module N Tributary Unit A full list of abbreviations used in timing and synchronization is listed in ETS 300 462-11. 4 Synchronization methods There are two fundamental methods of synchronizing nodal clocks. These are identified in

23、 ETS 300 462-1 l: - master-slave synchronization; - mutual synchronization. 4.1 Master-slave synchronization Master-slave synchronization is appropriate for synchronizing SDH networks and the following material offers guidance on using this method. Master-slave synchronization uses a hierarchy of cl

24、ocks in which each level of the hierarchy is synchronized with reference to a higher level. There are four qualities of clock in the synchronization hierarchy shown below: - Primary Reference Clock (PRC) ETS 300 462-6 5; - slave clock (transit node) under study; - slave clock (local node) under stud

25、y; - SDH Equipment Clock (SEC) ETS 300 462-5 4. The PRC is the highest quality hierarchical clock and the SEC is the lowest quality clock. Higher quality clocks must not be synchronised by lower quality clocks in holdover mode, but clocks in holdover mode can be used to synchronise clocks of the sam

26、e quality. There are limits on the number of clocks which can be connected in a synchronization distribution trail (see clause 8). Clock reference signals are distributed between levels of the hierarchy via a distribution network which may use the facilities of the transport network. The transport n

27、etwork may contain SECS. The distribution of timing between hierarchical node clocks shall be performed using a method which avoids intermediate pointer processing. Two possible methods are as follows: ETSI ETS*300*462- 2 96 W 3400855 a) recover timing from a received Synchronous Transport 0132898 T

28、87 Page 9 ETS 300 462-2: September 1996 Module N (STM-N) signal (this avoids the unpredictable effect of a pointer adjustment on the downstream slave clock ); b) derive timing from a synchronization trail that is not supported by a SDH network. The master-slave method uses a single-ended synchroniza

29、tion technique with the slave clock determining the synchronization trail to be used as its reference and changing to an alternative if the original trail fails. This is a unilateral control scheme. 4.2 Mutual synchronization The feasibility of employing mutual synchronization is left for further st

30、udy. The remainder of this ETS refers only to the hierarchical master-slave approach. 5 Functional description of clock types 5.1 Primary Reference Clock (PRC) A PRC is a stand-alone clock and a logical function which: - is either an autonomous clock; or - The PRC shall conform to ETS 300 462-5. it

31、accepts synchronization from a radio or satellite signal and performs filtering. 5.2 Synchronization Supply Unit (SSU) A SSU is a logical function which: - accepts synchronization inputs from a number of sources; - selects one of these inputs; - filters this sources clock; and - distributes the resu

32、ltant clock to other elements within a node. A functional diagram of the SSU is shown in figure 1 In the event of failure or degradation of all synchronization reference inputs, the SSU will use an internal timing source (under study). The physical implementation of this function may be integrated w

33、ithin a SDH network element, integrated within Public Switched Telephone Network (PSTN) switch, or as a stand-alone unit (a Stand-Alone Synchronization Equipment (SASE). ETSI ETS*300*462- 2 96 D 3400855 0332899 913 m Page 10 ETS 300 462-2: September 1996 - - - Inter- faces , I I- Select 71 Memory .

34、li li I: it i T4 i li 8. I; iexternaif :output I i . : I - - ,;9 1 TO . ssu 1 Key: TO: TI: T2: T3: T4: External timing output. Internal network element timing reference signal. Timing signal derived from STM-N input. Timing signal derived from 2 Mbit/s input. Timing signal derived from 2 MHz synchro

35、nization input. Where the SSU is integrated within a SDH Network Element (NE), TO should be provided. It may be possible to force the SSU into a free running condition. NOTE 1: NOTE 2: Figure 1 : The SSU clock function 5.3 SDH Equipment Clock (SEC) An SEC is the internal clock of an SDH network elem

36、ent and a logical function which; - accepts synchronization inputs from a number of sources within that element; - - The SDH clock is used to time the outgoing SDH STM-N interfaces of the network element. A functional diagram of the SEC is shown in figure 2. selects one of these inputs; filters this

37、 sources clock according to ETS 300 462-5 4. In the event of failure of all synchronization reference inputs the SEC shall use its own internal clock which shall conform to ETS 300 462-5 4. ETSI ETS*300*4b2- 2 9b 3400855 0332900 4b5 = Page 11 ETS 300 462-2: September 1996 ., i I -, il jT1 I/ I Selec

38、t B =7 i T2 11 jT3 1 Memory : - . Select A I I - TO ?.,Select c , T4 i faces :I i I :I SEC Key: TO: Intemal timing reference signal. T1: T2: T3: T4: External timing references. Timing signal derived from STM-N input. Timing signal derived from 2 Mbits input. Timing signal derived from 2 MHz synchron

39、ization input. terface NOTE 1: NOTE 2: This is a functional subset of the SETS as defined in ITU-T Recommendation G.783. It may be possible to force the SEC into a free running condition. Figure 2: The SEC clock function 6 Synchronization network architecture The architecture employed in SDH require

40、s the timing of all network element clocks to be traceable to a PRC. This clause details the target architecture for SDH network synchronization. Evolutionary aspects are discussed in clause 10. The distribution of synchronization can be categorized into intra-node within nodes containing a SSU and

41、inter-node as follows: a) intra-node distribution within nodes containing a SSU conforms to a logical star topology. All lower level network element clocks within a node boundary derive timing from the highest hierarchical clock level in the node. An exception may be made for the network element clo

42、ck that carries the synchronization trail to the SSU. An example illustrating this exception is given in the following: Assume that network timing has to be distributed along a ring structure where each node, in addition to the ring ADM, contains an SSU. By considering the ring ADMs to belong to a s

43、ynchronization trail rather than to the nodes where they are located, excessive cascading of SSUs can be prevented. All other outputs from each node may be timed from the local SSU. Apart from these network elements, only the clock of the highest hierarchical level in the node will recover timing fr

44、om synchronization links from other nodes. Timing is distributed from network elements within the boundary to network elements beyond the boundary via the SDH transmission medium. The relationship between clocks within a node is shown in figure 3. NOTE: Any interface used for synchronization of SDH

45、NE should comply with the requirements given in ETC 300 462-3 2. ETSI ETS*300*462- 2 96 3400855 CIL32901 3TL Page 12 ETS 300 462-2: September 1996 I J I i Logic al node bo un dary Figure 3: Synchronization network architecture for intra-node distribution b) inter-node distribution conforms to a tree

46、-like topology and enables all the nodes in the SDH network to be synchronized. The hierarchical relationship between clocks is shown in figure 4. With this architecture, it is important for the correct operation of the synchronization network that clocks of lower hierarchical level only accept timi

47、ng from clocks of the same or higher hierarchical level and that timing loops are avoided. To ensure that this relationship is preserved, the distribution network shall be designed such that, even under fault conditions, only valid higher level references are presented to hierarchical clocks. PRC PR

48、C: Primary Reference Clock Figure 4: Synchronization network architecture for inter-node distribution Clocks of a lower hierarchical level shall have a pull-in range which ensures that they can automatically acquire and lock to the timing signal generated by the same or higher level clock that they

49、are using as a reference. ETSI ETS*3aa*462- 2 96 m 3400855 0132702 238 = Page 13 ETS 300 462-2: September 1996 Phase reference information is transferred between synchronization nodes by means of a synchronization trail. When a trail becomes disabled then the node clock shall select another reference from a set of valid alternatives. When none exist, the node clock shall enter holdover mode. The synchronization trail is provided by one or more synchronization link connections each supported by a synchronized primary or secondar