DLA SMD-5962-95718 REV B-2007 MICROCIRCUIT DIGITAL CMOS LATCHUP RESISTANT PRIORITY INTERRUPT CONTROLLER MONOLITHIC SILICON《数字的互补金属氧化物半导体闭锁阻抗优先级中段控制器硅单片电路线型微电路》.pdf

《DLA SMD-5962-95718 REV B-2007 MICROCIRCUIT DIGITAL CMOS LATCHUP RESISTANT PRIORITY INTERRUPT CONTROLLER MONOLITHIC SILICON《数字的互补金属氧化物半导体闭锁阻抗优先级中段控制器硅单片电路线型微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-95718 REV B-2007 MICROCIRCUIT DIGITAL CMOS LATCHUP RESISTANT PRIORITY INTERRUPT CONTROLLER MONOLITHIC SILICON《数字的互补金属氧化物半导体闭锁阻抗优先级中段控制器硅单片电路线型微电路》.pdf（16页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R140-98. 98-07-27 Monica L. Poelking B Correct title to accurately describe device function. Update boilerplate to MIL-PRF-38535 requirements. - LTG 07-02-21 Thomas M. Hess REV SHET REV B SHET 15 REV STATUS REV

2、 B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Thomas Hess DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Thomas Hess COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APP

3、ROVED BY Monica L. Poelking AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 95-11-22 MICROCIRCUIT, DIGITAL, CMOS, LATCHUP RESISTANT PRIORITY INTERRUPT CONTROLLER, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-95718 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E

4、235-07 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95718 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents

5、two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assur

6、ance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 95718 01 V X C Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing num

7、ber 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA design

8、ator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 MD82C59A/7 Latchup resistant priority interrupt controller 1.2.3 Device class designator. The device class designator is a si

9、ngle letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualific

10、ation to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CDIP2-T28 28 Dual-in-line 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V

11、 or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95718 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97

12、1.3 Absolute maximum ratings. 1/ Supply voltage (VCC) +8.0 V dc Input or output voltage range (VIN, VOUT) GND -0.5 V dc to VCC+0.5 V dc Storage temperature range (TSTG) -65C to +150C Maximum power dissipation at +125C (PD). 1.06 W 2/ Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Therm

13、al resistance, junction-to-ambient (JA) 47C/W Lead temperature (soldering, 10 seconds). +275C Junction temperature (TJ). +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) 4.5 V dc to +5.5 V dc Ambient operating temperature range (TA). -55C to +125C Input low voltage range (VIL)

14、0.0 V dc to +0.8 V dc Input high voltage range (VIH). 2.2 V dc to VDD2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issue

15、s of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard

16、 Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from th

17、e Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, su

18、persedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ If device power exceeds packag

19、e dissipation capability, derate linearly (the derating is based on JA) at the following rate: 21.3 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95718 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43

20、218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The mo

21、dification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimen

22、sions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connec

23、tions. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.2.4 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 3. 3.3 Electrical performance characterist

24、ics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical

25、 test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SM

26、D PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for devi

27、ce class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix

28、A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufac

29、turer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requ

30、irements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provi

31、ded with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verifica

32、tion and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit

33、group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A).Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95

34、718 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxLogical 1 input voltage VIH

35、VCC= 5.5 V 1, 2, 3 All 2.2 V Logical 0 input voltage VILVCC= 4.5 V 1, 2, 3 All 0.8 V High output voltage VOH1VCC= 4.5 V, IOH= -2.5 mA 2/ 1, 2, 3 All 3.0 V High output voltage VOH2VCC= 4.5 V, IOH= -100.0 A 2/ 1, 2, 3 All VCC-0.4 V Low output voltage VOLVCC= 4.5 V, IOL= 2.5 mA 2/ 1, 2, 3 All 0.4 V Inp

36、ut leakage current IIVCC= 5.5 V VIN= GND or VCCPins 1-3, 26, 27 1, 2, 3 All -1.0 1.0 A Output leakage current IOZL, IOZHVCC= 5.5 V VOUT= GND or VCCPins 4-13, 15, 16 1, 2, 3 All -10 10 A IR input load current, low ILIRLVCC= 5.5 V, VIN= 0.0 V Pins 18-25 1, 2, 3 All -500 A IR input load current, high I

37、LIRHVCC= 5.5 V, VIN= 5.5 V Pins 18-25 1, 2, 3 All 10 A Standby power supply ICCSBOutputs open 3/ VCC= 5.5 V, VIN= VCCor GND 1, 2, 3 All 10 A Input capacitance CINVCC= open, f = 1 MHz All measurements referenced to device GND, see 4.4.1c 4 All 15 pF Output capacitance COUTVCC= open, f = 1 MHz All mea

38、surements referenced to device GND, see 4.4.1c 4 All 15 pF Input/output capacitance CI/OVCC= open, f = 1 MHz All measurements referenced to device GND, see 4.4.1c 4 All 15 pF Functional tests VCC= 4.5 V and VCC= 5.5 V See 4.4.1b 4/ 5/ 7, 8 All TIMING REQUIREMENTS AO/CS setup to RD/INTA tAHRL(1) 9, 1

39、0, 11 All 10 ns AO/CS hold after RD/INTA tRHAX(2) 9, 10, 11 All 5 ns RD/INTA pulse width tRLRH(3) 9, 10, 11 All 235 ns AO/CS setup to WR tAHWL(4) 9, 10, 11 All 0 ns AO/CS hold after WR tWHAX(5) 9, 10, 11 All 5 ns WR pulse width tWLWH(6) 9, 10, 11 All 165 ns Data setup to WR tDVWH(7) 9, 10, 11 All 24

40、0 ns Data hold after WR tWDHDX(8)9, 10, 11 All 5 ns Interrupt request tJLJH(9)9, 10, 11 All 100 ns Cascade setup to second or third INTA (slave only) tCVIAL(10)See figure 3. 6/ 7/ 9, 10, 11 All 55 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted

41、without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95718 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise spe

42、cified Group A subgroups Device type Limits Unit Min MaxTIMING REQUIREMENTS Continued. End of RD to next RD; End of INTA within an INTA sequence only tRHRL(11) 9, 10, 11 All 160 ns End of WR to next WR tWHWL(12) See figure 3. 6/ 7/ 9, 10, 11 All 190 ns End of command to next command (not same comman

43、d type) end of INTA sequence to next INTA sequence tCHCL(13) See figure 3. 6/ 7/ 8/ 9, 10, 11 All 500 ns Data valid from RD/INTA tRLDV(14) See figure 3. 6/ 7/ 9, 10, 11 All 160 ns Data float after RD/INTA tRHDZ(15) See figure 3. 7/ 9/ 9, 10, 11 All 10 100 ns Interrupt output delay tJHIH(16)9, 10, 11

44、 All 350 ns Cascade valid from first INTA (master only) tIALCV(17) 9, 10, 11 All 565 ns Enable active form RD or INTA tRLEL(18)9, 10, 11 All 125 ns Enable inactive form RD or INTA tRHEH(19) 9, 10, 11 All 60 ns Data valid from stable address tAHDV(20) 9, 10, 11 All 210 ns Cascade valid to valid data

45、tCVDV(21) See figure 3. 6/ 7/ 9, 10, 11 All 300 ns 1/ All testing to be performed using worst case test conditions, unless otherwise specified. 2/ Interchanging of force and sense conditions is permitted. 3/ Except for IR0-IR7, where VIN= VCCor open. 4/ Frequency defines the peripheral read/write cy

46、cle time. f = 1.25 MHz. 5/ Tested as follows: VIH= 2.6 V, VIL= 0.4 V, VOH 1.5 V, VOL 1.5 V. 6/ Tested as follows: f = 1 MHz, VIH= 2.6 V, VIL= 0.4 V, VOH 1.5 V, VOL 1.5 V, VCC= 4.5 V, test condition 2 in figure 3. 7/ See test condition 1 in figure 3. 8/ Worst case timing for tCHCLin actual system is

47、typically much greater than 400 ns. 9/ The parameters listed in the table are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after process and/or design changes. Provided by IHSNot for ResaleNo reproduction or netwo

48、rking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95718 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 Device type All Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CS WR RD D7D6D5D4D3D2D1D0CAS 0 CAS 1 GND 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CAS 2 SP/EN INT IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 INTA A0 VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or n