DLA SMD-5962-92118 REV N-2012 MICROCIRCUIT DIGITAL CMOS RADIATION HARDNENED MIL-STD-1553 SERIAL MICRO-CODED MONOLITHIC MULTI-MODE INTELLIGENT TERMINAL MONOLITHIC SILICON.pdf
《DLA SMD-5962-92118 REV N-2012 MICROCIRCUIT DIGITAL CMOS RADIATION HARDNENED MIL-STD-1553 SERIAL MICRO-CODED MONOLITHIC MULTI-MODE INTELLIGENT TERMINAL MONOLITHIC SILICON.pdf》由会员分享,可在线阅读,更多相关《DLA SMD-5962-92118 REV N-2012 MICROCIRCUIT DIGITAL CMOS RADIATION HARDNENED MIL-STD-1553 SERIAL MICRO-CODED MONOLITHIC MULTI-MODE INTELLIGENT TERMINAL MONOLITHIC SILICON.pdf(52页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R208-93. 93-08-06 Monica L. Poelking B Changes in accordance with NOR 5962-R187-94. 94-06-08 Monica L. Poelking C Add device type 02. Editorial changes throughout. 96-01-05 Monica L. Poelking D Changes in accor
2、dance with NOR 5962-R299-97. 97-05-29 Monica L. Poelking E Add device type 03. Editorial changes throughout. - TVN 98-06-29 Monica L. Poelking F In table IA: Add test conditions for IIN; change the limits for QIDD; remove the test condition VDD= 4.5 V for all the propagation delay tests; change the
3、limits for taand tiin memory read timing section; change the limits of tcin DMA timing section; and change the limit of tain JTAG timing section. Include pin connections for case outlines X and Z in radiation exposure connections. Editorial changes throughout. - TVN 98-09-18 Monica L. Poelking G In
4、table I, change IINlimits; add a footnote to QIDD; add tcin power-up master reset timing section. Correct the JTAG timing waveforms. TVN 99-05-26 Monica L. Poelking H Add device type 04. Editorial changes throughout. TVN 00-07-18 Monica L. Poelking J Add notes to memory write and memory read wavefor
5、ms. Add figure B-1 to appendix A. Editorial changes throughout. TVN 01-03-15 Thomas M. Hess K Update boilerplate to MIL-PRF-38535 requirements, to include radiation hardness assurance requirements. CFS 07-07-30 Thomas M. Hess L Correct die thickness in appendix A. Correct high level output voltage t
6、est condition IOH in table IA. Correct address bus pins (A5-A15) description and add footnote 4/ in table III. Update electrical test requirements for group C and group D in table IIA. - MAA 11-06-07 David J. Corbett M Correct package type Y case outline dimensions A1 and L in figure 1. - MAA 11-11-
7、14 Thomas M. Hess N Add MIL-STD-1553 protocol stress test (Fstress) and add footnote10 / to table IA MAA 12-05-08 Thomas M. Hess REV N N N N N N N N N N N N N N N N SHEET 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 REV N N N N N N N N N N N N N N N N N N N N SHEET 15 16 17 18 19 20 21 22 23 24 2
8、5 26 27 28 29 30 31 32 33 34 REV STATUS OF SHEETS REV N N N N N N N N N N N N N N SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Thomas M. Hess DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR U
9、SE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Thomas M. Hess APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, CMOS, RADIATION HARDNENED, MIL-STD-1553 SERIAL MICRO-CODED MONOLITHIC MULTI-MODE INTELLIGENT TERMINAL, MONOLITHIC SILICON DRAWING APPROVAL DATE 93-
10、06-07 REVISION LEVEL N SIZE A CAGE CODE 67268 5962-92118 SHEET 1 OF 50 DSCC FORM 2233 APR 97 5962-E280-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-92118
11、REVISION LEVEL N SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in
12、the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 H 92118 01 V X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device c
13、lass designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the M
14、IL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 UT69151 MIL-STD-1553 bus controll
15、er, remote terminal, monitor interface 02 UT69151E MIL-STD-1553 bus controller, remote terminal, monitor interface radiation hardened 03 UT69151E MIL-STD-1553 bus controller, remote terminal, monitor interface 04 UT69151C MIL-STD-1553 bus controller, remote terminal, monitor interface radiation hard
16、ened 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in acco
17、rdance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA3-P84 84 Pin grid array Y See figure 1 84 Lea
18、ded chip carrier Z See figure 1 132 Leaded chip carrier with unformed leads, nonconductive tier bar 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networki
19、ng permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-92118 REVISION LEVEL N SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VDD) -0.3 V dc to +7.0 V dc Voltage on any pin . -0.3 V dc t
20、o VCC+ 0.3 V dc Latchup immunity (ILU) . 150 mA DC input current (II) 10 mA Maximum power dissipation (PD) . 2.5 W Storage temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 5 seconds) +300C Thermal resistance, junction-to-case (JC) . 15C/W Maximum junction temperature (TJ) . 175C
21、 1.4 Recommended operating conditions. Supply voltage range (VDD) +4.5 V dc to +5.5 V dc DC input voltage (VIN) 0 V dc to VDDMaximum input voltage (VIL). 0.8 V dc Maximum input voltage, 24 MHz input (VILC) . 0.3 VDDMinimum input voltage (VIH) . 2.2 V dc Minimum input voltage, 24 MHz input (VIHC) 0.7
22、 VDDOperating frequency (fIN) 24 0.01% MHz Duty cycle (DC). 50 5% Case operating temperature range (TC) . -55C to +125C 1.5 Radiation features: Maximum total dose available (dose rate = 50 300 rads(Si)/s): Device type 02 . 1 x 106rads (Si) Device type 04 . 300K rads (Si) Single event phenomena (SEP)
23、: No SEU occurs at effective LET (see 4.4.4.5): Device type 02 47 MeV/(mg/cm2) 2/ Device type 04 14.4 MeV/(mg/cm2) 2/ No SEL occurs at effective LET (see 4.4.4.5): Device type 02 136 MeV/(mg/cm2) 2/ Device type 04 128 MeV/(mg/cm2) 2/ Dose rate upset (20 ns pulse) 2/ 3/ Dose rate latchup . 2/ 3/ Dose
24、 rate survivability 2/ 3/ Neutron irradiation . 2/ 3/ 1.6 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) . 95.12 percent _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device
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