DLA DSCC-VID-V62 12616-2012 MICROCIRCUIT DIGITAL 1024-POSITION DIGITAL POTENTIOMETER WITH MAXIMUM % R-TOLERANCE ERROR AND 20-TP MEMORY MONOLITHIC SILICON.pdf

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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil Original dat

2、e of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, 1024-POSITION, DIGITAL POTENTIOMETER WITH MAXIMUM 1% R-TOLERANCE ERROR AND 20-TP MEMORY, MONOLITHIC SILICON 12-04-09 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12616 REV PAGE 1 OF 15 AMSC N/A 5962-V0

3、48-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12616 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 1024-positio

4、n, digital potential meter with maximum 1% R-tolerance error and 20-TP memory microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an adminis

5、trative control number for identifying the item on the engineering documentation: V62/12616 - 01 X B Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 AD5292-EP 1024-position, digital potential meter

6、with maximum 1% R-tolerance error and 20-TP memory 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 JEDEC MO-153-AB Lead thin Shrink Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or o

7、ther lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBU

8、S, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12616 REV PAGE 3 1.3 Absolute maximum ratings. 1/ VDDto GND . -0.3 V to +35 V VSSto GND +0.3 V to -25 V VLOGICto GND . -0.3 V to +7 V VDDto VSS35 V VA, VB, VWto GND . VSS-0.3 V, VDD+ 0.3 V Digital input and output voltage to GND -0.3 V to VLOGIC+ 0.3 V

9、 EXT_CAP voltage to GND -0.3 V to +7 V IA, IB, IW Continuous . 3 mA Pulsed 2/ Frequency 10 kHz 3/d 3/ Frequency 10 kHz . 3/d 3/ Operating temperature range 4/ -55C to +125C Maximum Junction Temperature Range (TJmax) . 150C Storage temperature range . -65C to 150C Reflow soldering Peak temperature 26

10、0C Time at peak temperature . 20 sec to 40 sec Package power dissipation . (TJmax TA)/JAThermal resistance Case outline JAJAUnit Case X 93 5/ 20 C/W 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-7 High

11、 Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 1/ Stresses beyond those listed under “absol

12、ute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for exte

13、nded periods may affect device reliability. 2/ Maximum terminal current is bounded by the maximum current handling of the switches, maximum poser dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 3/ Pulse duty factor. 4/ Includ

14、es programming of OTP memory. 5/ JEDEC 2S2P test board, still air (0 m/sec to 1 m/sec air flow). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12616 REV PAGE 4 3. REQUIREM

15、ENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the ma

16、nufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The de

17、sign, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be

18、 as shown in figure 3. 3.5.4 Functional block diagram. The functional block diagram shall be as shown in figure 4. 3.5.5 Shift register content. The shift register content shall be as shown in figure 5. 3.5.6 Write timing diagram. The write timing diagram shall be as shown in figure 6. 3.5.7 Read ti

19、ming diagram. The read timing diagram shall be as shown in figure 7. 3.5.8 Resistor position nonlinearity error. The resistor position nonlinearity error shall be as shown in figure 8. 3.5.9 Potentiometer divider nonlinearity error. The potentiometer divider nonlinearity error shall be as shown in f

20、igure 9. 3.5.10 Wiper resistance. The wiper resistance shall be as shown in figure 10. 3.5.11 Power supply sensitivity. The power supply sensitivity shall be as shown in figure 11. 3.5.12 Gain vs frequency. The gain vs frequency shall be as shown in figure 12. 3.5.13 Common mode leakage current. The

21、 common mode leakage current shall be as shown in figure 13. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12616 REV PAGE 5 TABLE I. Electrical performance characteristics

22、. 1/ Test Symbol Conditions 2/ Limits Unit Min Max DC characteristics Rheostat mode Resolution N 10 Bits Resistor differential nonlinearity 4/ R-DNL RWB, VA= NC -1 +1 LSB Resistor integral nonlinearity 4/ R-INL RAB= 20 k, |VDD VSS| = 26 V to 33 V -2 +2 RAB= 20 k, |VDD VSS| = 26 V to 33 V -3 +3 Nomin

23、al resistor tolerance (R-Perf mode) 5/ RAB/RAB7/ -1 +1 % Nominal resistor tolerance (Normal mode) 6/ RAB/RAB7 TYP 3/ Resistance temperature coefficient (RAB/RAB)T x10635 TYP 3/ ppm/C Wiper resistance RW100 DC characteristics Potentiometer divider mode Resolution N 10 Bits Differential nonlinearity 8

24、/ DNL -1 +1 LSB Integral nonlinearity 8/ INL -2.5 +2.5 Voltage divider temperature coefficient 6/ (VW/VW)T x106Code = half scale; 5 TYP 3/ ppm/C Full scale error VWFSECode = full scale -8 +1 LSB Zero scale error VWZSECode = zero scale 0 10 Resistor terminals Terminal voltage range 9/ VA, VB, VWVSSVD

25、DV Capacitance A, Capacitance B 6/ CA, CBf = 1 MHz, measured to GND, code = half scale 85 TYP 3/ pF Capacitance W 6/ CW65 TYP 3/ Common mode leakage current 6/ ICMVA= VB= VW-120 +120 nA Digital inputs Input logic high 6/ VIHVLOGIC= 2.7 V to 5.5 V 2.0 V Input logic low 6/ VIL LOGIC= 2.7 V to 5.5 V 0.

26、8 Input current IILVIN= 0 V or VLOGIC1 A Input capacitance 6/ CIL5 TYP 3/ pF See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12616 REV PAGE 6 T

27、ABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ Limits Unit Min Max Digital output (SDO and RDY) Output high voltage 6/ VOHRPULL_UP = 2.2 k to VLOGICVLOGIC 0.4 V Output low voltage 6/ VOLGND + 0.4 Three state leakage current -1 +1 A Output capacitance 6/ COL5

28、 TYP 3/ pF Power supplies Single supply power range VDDVSS= 0 V 9 33 V Dual supply power range VDD/VSS9 16.5 V Positive supply current IDDVDD/VSS= 16.5 V 2 A Negative supply current ISSVDD/VSS= 16.5 V -2 A Logic supply range VLOGIC2.7 5.5 V Logic supply current ILOGICVLOGIC=5 V, VIH= 5 V or VIL= GND

29、 10 A OTP store current 6/ 10/ ILOGC_PROGVIH= 5 V or VIL= GND 25 TYP 3/ mA OTP read current 6/ 11/ ILOGIC_FUSE_READVIH= 5 V or VIL= GND 25 TYP 3/ mA Power dissipation 12/ PDISSVIH= 5 V or VIL= GND 110 W Power supply rejection ratio PSSR VDD/VSS= 15 V 10% 0.103 TYP 3/ %/% Dynamic characteristics 8/ 1

30、3/ Bandwidth BW -3 dB 520 TYP 3/ Total harmonic distortion THDWVA= 1Vrms, VB= 0, f = 1 kHz -93 TYP 3/ VWsetting time ts VA = 30 V, VB = 0 V, 0.5 LSB error band, initial code = zero scale, board capacitance = 170 pF Code = full scale, normal mode Code = full scale, R-perf mode Code = half scale, norm

31、al mode Code = half scale, R-Perf mode 750 TYP 3/ 2.5 TYP 3/ 2.5 TYP 3/ 5 TYP 3/ ns s s s Resistor noise density eN_WBCode = half scale 10 TYP 3/ nV/Hz See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIM

32、E COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12616 REV PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 14/ Limits 15/ Unit Min Max Interface timing specifications SCLK cycle time t116/ 20 ns SCLK high time t2 10 SCLK low time t3 10 SYNCnullnull

33、nullnullnullnullnullto SCLK falling edge setup time t4 10 Data setup time t5 5 Data hold timw t6 5 SCLK falling edge to SYNCnullnullnullnullnullnullnullrising edge t7 1 Minimum SYNCnullnullnullnullnullnullnullhigh time t8 400 17/ SYNCnullnullnullnullnullnullnullrising edge to next SCLK fall ignore t

34、9 14 RDY rising edge to SYNCnullnullnullnullnullnullnullfalling edge t1018/ 1 SYNCnullnullnullnullnullnullnullrising edge to RDY fall time t1118/ 40RDY low time, RDAC register write command execute time (R-Perf mode) t1218/ 2.4 s RDY low time, RDAC register write command execute time (normal mode) 4

35、19 ns RDY low time, memory program execute time 8 ms Software/hardware reset 1.5 ms RDY low time, RDAC register readback execute time t1318/ 450 ns RDY low time, memory readback execute time 1.3 ms SCLK rising edge to SDO valid t1418/ 450 ns Minimum RESETnullnullnullnullnullnullnullnullnullpulse wid

36、th (asynchronous) tRESET20 ns Power on OTP restore time tPOWER-UP 19/ 2ms See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12616 REV PAGE 8 TABL

37、E I. Electrical performance characteristics Continued. 1/ 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parame

38、ters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ VDD = 21 V to 33 V, VSS= 0V; VDD= 10.5 V to 16.5 V, VSS= -10.5 V to -16.5 V; VLOGIC= 2.7 V to 5.5 V, VA= VDD, VB= VSS, -55C TA +125C, unless otherwi

39、se noted. 3/ Typical values represent average readings at 25C, VDD= 15 V, VSS= -15 V, and VLOGIC= 5V. 4/ Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between RWBat code 0x00B and code 0x3FF or between RWAat code 0x3F3 and code 0x000. R-DNL measures the re

40、lative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with a wiper current of 1 mA for VA 12 V and 1.2 mA for VA 12 V. 5/ Resistor performance mode. The terms resistor performance mode and R-Perf mode are used interchangeably. 6

41、/ Guaranteed by design and characterization, not subject to production test. 7/ Resistor performance mode code range Resistor Tolerance per Code -55C TA +125C |VDDVSS| = 30 V to 33V |VDDVSS| = 26 V to 30V |VDDVSS| = 22 V to 26V |VDDVSS| = 21 V to 22V RWBRWARWBRWARWBRWARWBRWA1% R-Tolerance From 0x1EF

42、 to 0x3FF From 0x000 to 0x210 From 0x1F4 to 0x3FF From 0x000 to 0x20B From 0x1F4 to 0x3FF From 0x000 to 0x20B N/A N/A 2% R-Tolerance From 0x0C3 to 0x3FF From 0x000 to 0x33C From 0x0E6 to 0x3FF From 0x000 to 0x319 From 0x131 to 0x3FF From 0x000 to 0x2CE From 0x131 to 0x3FF From 0x000 to 0x2CE 3% R-To

43、lerance From 0x073 to 0x3FF From 0x000 to 0x38C From 0x087 to 0x3FF From 0x000 to 0x378 From 0x0AF to 0x3FF From 0x000 to 0x350 From 0x0AF to 0x3FF From 0x000 to 0x350 8/ INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA= VDDand VB

44、= 0V. DNL specification limits of 1 LSB maximum guaranteed monotonic operating conditions. 9/ Resistor terminal A, Resistor terminal B, and Resistor terminal W, have no limitations on polarity with respect to each other. Dual supply operation enables ground referenced bipolar signal adjustment. 10/

45、Different from operating current; supply current for fuse program lasts approximately 550 s. 11/ Different from operating current; supply current for fuse read lasts approximately 550 s. 12/ PDISSis calculated from (IDDx VDD) + (ILOGICx VLOGIC). 13/ All dynamic characteristics use VDD= 15 V, VSS= -1

46、5 V, and VLOGIC= 5 V. 14/ VDD/VSS= 15 V, VLOGIC = 2.7 V to 5.5 V, -55C TA +125C. All specifications TMINto TMAX, unless otherwise noted. 15/ All input signal are specified with tR= tF= 1ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL+VIH)/2. 16/ Maximum SCLK frequency is 50 MHz. 17/

47、Refer to t12 and t13 for RDAC register and memory commands operations. 18/ RPULL-UP = 2.2 k to VLOGIC, with a capacitance load of 186 pF. 19/ Maximum time after VLOGICis equal to 2.5 V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MAR

48、ITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12616 REV PAGE 9 Case X Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max A 1.20 E 4.30 4.50 A1 0.05 0.15 E1 6.40 BSC b 0.19 0.30 e 0.65 BSC c 0.09 0.20 L 0.45 0.75 D 4.90 5.10 NOTES: 1. All linear dimensions are in millimeters. 2. Falls within JEDEC MO-153-A