DLA DSCC-VID-V62 09630-2009 MICROCIRCUIT DIGITAL-LINEAR IMPROVED 8-CHANNEL DUAL 4-CHANNEL CMOS ANALOG MULTIPLEXERS MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing Y
2、Y MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL-LINEAR, IMPROVED, 8-CHANNEL/DUAL 4-CHANNEL, CMOS ANALOG MULTIPLEXERS, MONOLITHIC SILICON 09-09-16 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09630 REV PAGE 1 OF 14 AMSC N/A 5962-V079-09 Provided by IHSNot for Resal
3、eNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09630 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of an improved, 8-channel/Dual 4-channel, CMOS analog mult
4、iplexers microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering do
5、cumentation: V62/09630 - 01 X B Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 DG408 8-channel, CMOS analog multiplexer 02 DG409 Dual 4-channel, CMOS analog multiplexer 1.2.2 Case outline(s). The c
6、ase outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 JEDEC MS012 Small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin
7、-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09630 REV PAGE 3 1.3 Absolute maximum ratings.
8、1/ Voltage V+ -0.3 V to 44 V GND -0.3 V to 25 V Digital input, S, D (V- - 2V) to (V+ + 2V) or 30 mA (which ever occurs first) 2/ Continuous current (any terminal) . 30 mA Peak current, S, D (pulsed at 1 ms, 10% duty cycle max) 100 mA Operating temperature range -55C to +125C Storage temperature rang
9、e . -55C to +150C Junction temperature +150C Lead temperature (soldering , 10 sec) +300C Electro Static Discharge (ESD) Human Body Model (HBM) 2000 V Class 1C Moisture Sensitive Level (MSL) . Level 1 1.4 Thermal data table. Case outline letter X X Units PC Board Single Layer Multi-Layer 3/ Power dis
10、sipation (PD), maximum at +70C 696 1096 mW Power dissipation (PD) derating above +70C 8.7 13.7 mW/C Thermal resistance, junction to case (JC) 32 23 C/W Thermal resistance, junction to ambient (JA) 115 73 C/W 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devi
11、ces JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 1/ Stresses beyond those listed under “a
12、bsolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for
13、extended periods may affect device reliability. 2/ Signals on S_, D_, EN, A0, A1, or A2 exceeding V+ or V- are clamped by internal diodes. Limit forward current to maximum current ratings. 3/ Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using
14、a four-layer board. For detailed information on package thermal considerations, refer to manufacturers website Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/0963
15、0 REV PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container sha
16、ll be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and ph
17、ysical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Truth table. The truth ta
18、ble shall be as shown in figure 3. 3.5.4 Functional diagram. The functional diagram shall be as shown in figure 4. 3.5.5 Test circuits and timing waveforms. 3.5.5.1 Transition time. The transition time shall be as shown in figure 5. 3.5.5.2 Enable switching time. The enable switching time shall be a
19、s shown in figure 6. 3.5.5.3 Break before make interval. The break before make interval shall be as shown in figure 7. 3.5.5.4 Charge injection. The charge injection shall be as shown in figure 8. 3.5.5.5 Off isolation. The off isolation shall be as shown in figure 9. 3.5.5.6 Cross talk. The cross t
20、alk shall be as shown in figure 10. 3.5.5.7 Source and drain capacitance. The source and drain capacitance shall be as shown in figure 11. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDEN
21、T NO. 16236 DWG NO. V62/09630 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions Device type: All 2/ TALimits 3/ Unit Min Max DUAL SUPPLIES Switch Analog signal range VANALOG4/ -15 15 V Drain source on resistance rDS(ON)IS= -1.0 mA, VD= 10 V 25C 100 -55C to 125C 12
22、5 On resistance matching between channels rDS(ON)IS= -1.0 mA, VD= 10 V 5/ 25C 8 -55C to 125C 10 On resistance flatness rFLATIS= -1.0 mA, VD= 5 V or 0 V 25C 9 -55C to 125C 12 Source off leakage current 6/ IS(OFF)VD= 10 V, VS= 10 V, VEN= 0 V 25C -0.5 0.5 nA -55C to 125C -50 50 Drain off leakage curren
23、t 6/ ID(OFF)VD= 10 V, VS= 10 V, VEN= 0 V Device type 01 25C -1 1 nA -55C to 125C -100 100 Device type 02 25C -1 1 -55C to 125C -50 50 Drain on leakage current 6/ ID(ON)VD= 10 V, VS= 10 V, sequence each switch on Device type 01 25C -1 1 nA -55C to 125C -100 100 Device type 02 25C -1 1 -55C to 125C -5
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