JEDEC JESD79-3-3-2013 3D Stacked SDRAM (Addendum No 3 to JESD79 3).pdf

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1、DECEMBER 2013Addendum No. 3 to JESD79-3:3D Stacked SDRAMJEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJEDECSTANDARDJESD79-3-3NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and appr

2、oved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining

3、with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or proc

4、esses. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and app

5、lication, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless a

6、ll requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative contact information. Published

7、 by JEDEC Solid State Technology Association 2014 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resul

8、ting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Ar

9、lington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. (This page is intentionally left blank)JESD79-3-3-i-TABLE OF CONTENTS1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10、 . . . . . . . 11.1 Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3DS SDRAM Package Pinout and Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.1 Overview. . . . . . . . . . . .

11、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.2 3D Stacked / DDR3 SDRAM x4 Ballout using MO-207. . . . . . . . . . . . . . . . . . . . . . . . . . 42.3 3D Stacked / DDR3 SDRAM x8 Ballout using MO-207. . . . . . . . . . . . . . . . . . . . .

12、. . . . . 52.4 Logical Rank Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.5 3D Stack Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.6 3DS SDRAM System Addressin

13、g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.7 DDR3 3DS Stack Addressing Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.8 Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14、. . . . . . . . . . . . . . . . . . . . . 113 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.1 Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15、. . . 133.2 Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3 Reset Signal and Initialization Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.4 Mode Register Definition . . . .

16、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 SDRAM Command Description and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.1 Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17、 . . . . . . . . . . . . . . . . . . 174.2 ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.3 Precharge and Precharge All Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.4 Read and Writ

18、e Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.5 Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.6 Self-Refresh Operation and Power-Down Modes . . . . . . . .

19、 . . . . . . . . . . . . . . . . . . . . . . 224.7 ZQ Calibration Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 On Die Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20、. . . 256 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 AC this will be done independently of external clocks. All steps in the JESD79-3 initialization sequence must be followed. No additional steps are required for 3

21、DS DDR3 devices but the unique nature of 3DS devices (which have a single external I/O structure shared by all logical ranks of the entire device) has to be considered when programing the SDRAM mode register bits (see next section for details).JESD79-3-3Page 143.4 Mode Register DefinitionLike planar

22、 DDR3 SDRAMs, DDR3 3D Stacked SDRAMs have four Mode Registers. One set of registers controls the entire stack regardless if the 3DS stack has two, four or eight logical ranks, and they must be programmed via a Mode Register Set (MRS) command.For 3DS DDR3 stacks configured as n logical ranks, the sin

23、gle set of MRS registers is addressed by CS0_n as shown in Table 5.Table 5 Simplified Truth Table for MRS CommandDRAM Command CS0_n CS1_n CS2_n CS3_n CIDLogical rank 0Logical rank 1Logical rank 2Logical rank 3Logical rank 4Logical rank 5Logical rank 6Logical rank 7NotesMode Register SetL V V V V MRS

24、 MRS MRS MRS MRS MRS MRS MRS1 2Mode Register Set H V V V VDES or NOPDES or NOPDES or NOPDES or NOPDES or NOPDES or NOPDES or NOPDES or NOP2Any Command H H H H V DES DES DES DES DES DES DES DES 2Programming the register fields for a stacked device has some special considerations. Waiting for the timi

25、ng parameter tMRD is required between two MRS commands issued to any logical rank in a stacked device. After an MRS command is given, waiting for tMOD is required before a non-MRS command can be given to any logical rank in the stack. The mode register MR0 stores the data for controlling various ope

26、rating modes of DDR3 SDRAM. Due to the additional latency caused by stacking multiple memory dies, one additional CAS Latency setting (CL-15), which was not used in the JESD79-3 base specification, has been added to the MR0 bits A6:4, as shown in Figure 7. 1. Mode Register Set to all logical ranks2.

27、 “V” means H or L (but a defined logic level)JESD79-3-3Page 15BA2 BA1 BA0 A15 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field010 001PPD WR DLL TM CL RBT CL BL Mode Register 0A6 A5 A4 A2 CL0 0 0 0 Reserved0 0 1 0 Reserved for CL5 of non-3D device0 1 0 0 60 1 1 0 71 0 0 0 81 0 1 0 91 1 0 0

28、 101 1 1 0 110 0 0 1 120 0 1 1 130 1 0 1 140 1 1 1 151 0 0 1 Reserved1 0 1 1 Reserved1 1 0 1 Reserved1 1 1 1 ReservedFigure 7 Mode Register 0 DefinitionIn MR1, Additive Latency (AL) of CL-3 is supported for the case that tAA is larger than tRCD (optional if tAA=tRCD), as shown in Figure 8. BA2 BA1 B

29、A0A15 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field010 101Qoff TDQS01Rtt_Nom01Level Rtt_Nom D.I.C. AL Rtt_Nom D.I.C. DLLMode Register 1A4 A3 Additive Latency0 0 0 (AL disabled)0 1 CL-11 0 CL-21 1CL-32Figure 8 Mode Register 1 Definition1. Must be programmed to 01. Must be programmed to

30、02. For devices supporting the DDR3-1066F-3DS1B, DDR3-1333H-3DS1B, DDR3-1600K-3DS1B and DDR3-1866M-3DS1B speed bins, support for AL=CL-3 is optionalJESD79-3-3Page 16Mode registers 2 to 3 are identical to the equivalent mode registers in planar DDR3 SDRAMs.As the default values of the Mode Registers

31、(MR#) are not defined, the contents of Mode Registers must be fully initialized and/or re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers can be altered by re-executing the MRS command during normal operation. When programming the

32、mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be redefined when the MRS command is issued. MRS commands do not affect array contents, which means these commands can be executed any time after power-up wi

33、thout affecting the array contents.JESD79-3-3Page 174 SDRAM Command Description and Operation4.1 Write LevelingThe host initiates write leveling mode to all SDRAMs by setting bit 7 of MR1 to 1. Upon entering write leveling mode, the DQ pins are in undefined driving mode. During write leveling mode,

34、only NOP or DESELECT commands are allowed, as well as an MRS command to exit write leveling mode.Since a 3DS SDRAM configured as n logical ranks only has one physical set of output devices in the master die, the host only performs write leveling to one of the logical ranks in the package rank and do

35、esnt need to perform write leveling to the other logical ranks. Therefore the host write levels one package rank at a time, and the outputs of other package ranks must be disabled by setting MR1 bit A12 to 1 in all other package ranks (which could be comprised of 3D Stacked devices or planar devices

36、) on the same channel, which requires the host to be aware of what ranks in the channel are associated with individual package ranks.4.2 ACTIVE CommandIn a 3D Stacked DDR3 SDRAM the four chip select pins and the CID pin select the logical rank. No more than one logical rank ACTIVE command can be ini

37、tiated simultaneously to DDR3 3DS devices, i.e. no more than a single chip select can be active when a ACTIVE command is send to a 3DS device, as shown in Table 6.The minimum time interval between successive ACTIVE commands to the same bank of a DDR3 SDRAM is defined by tRC. The minimum time interva

38、l between successive ACTIVE commands to different banks of a DDR3 SDRAM is defined by tRRD.For a 3DS device, the timing parameter that applies to successive ACTIVE commands to different banks in the same logical rank is defined as tRRD_slr (MIN). The timing parameter that applies to successive ACTIV

39、E commands to different logical ranks is defined as tRRD_dlr (MIN).No more than four bank ACTIVE commands may be issued in a given tFAW_slr (MIN) period to the same logical rank. For all logical ranks in a 3DS device, the tFAW_dlr timing constraint applies, i.e. no more than four bank ACTIVE command

40、s to the whole 3DS SDRAM may be issued in a given tFAW_dlr (MIN) period.The timing restrictions covering ACTIVE commands are documented in “Electrical Characteristics and AC Timings” on page 63.JESD79-3-3Page 18Table 6 Truth Table for ACTIVE CommandDRAM CommandCS0_n CS1_n CS2_n CS3_n CIDLogical rank

41、 0Logical rank 1Logical rank 2Logical rank 3Logical rank 4Logical rank 5Logical rank 6Logical rank 7NotesActive (ACT) L H H H L ACT DES DES DES DES DES DES DESActive (ACT) H L H H L DES ACT DES DES DES DES DES DESActive (ACT) H H L H L DES DES ACT DES DES DES DES DESActive (ACT) H H H L L DES DES DE

42、S ACT DES DES DES DESActive (ACT) L H H H H DES DES DES DES ACT DES DES DESActive (ACT) H L H H H DES DES DES DES DES ACT DES DESActive (ACT) H H L H H DES DES DES DES DES DES ACT DESActive (ACT) H H H L H DES DES DES DES DES DES DES ACTActive (ACT) V V L L V illegal1Active (ACT) V L V L V illegal1A

43、ctive (ACT) L V V L V illegal1Active (ACT) V L L V V illegal1Active (ACT) L V L V V illegal1Active (ACT) L L V V V illegal1Any CommandH H H H V DES DES DES DES DES DES DES DES14.3 Precharge and Precharge All CommandsThe Single Bank Precharge (PRE) and Precharge All Banks (PREA) commands apply only t

44、o selected logical ranks of a 3D Stacked SDRAM. It means that these commands are allowed to be issued to multiple ranks (four logical ranks maximum) at the same time (broadcast command). And it is illegal to issue PREA commands to multiple logical ranks simultaneously if they have more than 8 open r

45、ows in total.The bank(s) will be available for a subsequent row activation a specified time (tRP) after the Precharge command is issued, except in the case of concurrent auto precharge, where a Read or Write command to a different rank is allowed as long as it does not interrupt the data transfer in

46、 the current bank and does not violate any other timing parameters in a logical rank.PRE commands (or PRE commands to each open bank) have to be issued to all logical ranks with open banks before the device can enter Self Refresh mode.A Precharge command is allowed if there is no open row in that ba

47、nk (idle state) of the selected logical rank(s) or if the previously open row is already in the process of precharging. However, the precharge period will be determined by the last Precharge command issued to the bank of the selected logical rank(s).Each logical rank of 3D Stacked SDRAMs has the sam

48、e values for tRP, tRTP, tRAS and tDAL as planar DDR3 SDRAMs of the same frequency.Table 7 and Table 8 show the truth tables for Precharge and Precharge All commands.1. “V” means H or L (but a defined logic level)JESD79-3-3Page 19Table 7 Truth Table for Precharge CommandDRAM CommandCS0_n CS1_n CS2_n

49、CS3_n CIDLogical rank 0Logical rank 1Logical rank 2Logical rank 3Logical rank 4Logical rank 5Logical rank 6Logical rank 7NotesPrecharge (PRE) L L L L L PRE PRE PRE PRE DES DES DES DES1 21. Precharge only to the same selected bank within selected logical rank(s)Precharge (PRE) L L L H L PRE PRE PRE DES DES DES DES DES1 2Precharge (PRE) L L H L L PRE PRE DES PRE DES DES DES DES1 2Precharge (PRE) L L H H L PRE PRE DES DES DES DES DES DES1 2Precharge (PRE) L H L L L PRE DES PRE PRE DES DES DES DES1 2Precharge (PRE) L H L H L PRE DES PRE DES DES DES DES DES1 2Precharge (PRE) L H