JEDEC JESD22-B109B-2014 Flip Chip Tensile Pull.pdf

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1、JEDEC STANDARD Flip Chip Tensile Pull JESD22-B109B (Revision of JESD22-B109A, January 2009) JULY 2014 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subseq

2、uently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in

3、selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or arti

4、cles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to produ

5、ct specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this stand

6、ard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative contac

7、t information. Published by JEDEC Solid State Technology Association 2014 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge

8、 for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th S

9、treet Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 22-B109B -i- Test Method B109B (Revision of Test Method B109A) TEST METHOD B109B FLIP CHIP TENSILE PULL Foreword This test is performed assess the integrity of

10、 the solder bump interconnection between the flip chip die and the substrate. Flip chip tensile pull is a destructive test. JEDEC Standard No. 22-B109B Test Method B109B -ii- (Revision of Test Method B109A) JEDEC Standard No. 22-B109B Page 1 Test Method B109B (Revision of Test Method B109A) TEST MET

11、HOD B109B FLIP CHIP TENSILE PULL (From JEDEC Board Ballot JCB-14-28, formulated under the cognizance of the JC-14.1 Subcommittee on Reliability Test Methods for Packaged Devices.) 1 Scope This test method is applicable to flip chip die after the die and substrate solder joint is formed, but prior to

12、 application of underfill or other materials that increase the apparent bond strength. It should be used to assess the consistency and quality of the chip join process and solder joint integrity across a given flip chip die. This method covers both Pb and Pb-free solder bumps. NOTE Considering that

13、this is a destructive test, it may be not suitable for qualification or process development where medium to high volume sampling might be necessary. In manufacturing, this test can be used to compare to original baseline results. 2 Terms and definitions 2.1 backside of flip chip die: The surface of

14、the device opposite the face to which the solder bump interconnections are attached. 2.2 crosshead: The pulling jig on the tensile pull tool. 2.3 delamination: A failure found during tensile pull of flip chip solder joints wherein the solder bump interconnection metallurgy is at least partially remo

15、ved from either the substrate or die, with the solder bump remaining continuous. 2.4 die fracture: A failure found during tensile pull of flip chip solder joints wherein the body of the die is fractured and damaged before all the solder bumps are separated. 2.5 die-pad fracture: A fracture in the di

16、e far-back-end-of-line (FBEOL) die structure. 2.6 flip chip die: An unpackaged die whose interconnection to a substrate is formed through solder joints. 2.7 interconnect: The resulting solder connection between device and substrate after reflow. 2.8 intermetallic fracture: A failure found during ten

17、sile pull of flip chip solder joints wherein any portion of the fracture surface occurs at an intermetallic formed between the solder and the device or substrate metallurgy. JEDEC Standard No. 22-B109B Page 2 Test Method B109B (Revision of Test Method B109A) 2 Terms and definitions (contd) 2.9 nonwe

18、t solder bumps: A solder bump that does not make bond to the substrate pad metallurgy during the solder reflow process. NOTE A nonwet solder bump is detected as an area on the substrate pad where, after tensile pull, the substrate pad metallurgy displays the original color and texture with no eviden

19、ce of solder fusion. Depopulated areas, where no solder joint formation is expected, are excluded. 2.10 passivation-to-UBM fracture: A fracture between the passivation and the solder under-bump metallurgy (UBM). 2.11 planar fracture: A fracture within the under-bump metallurgy (UBM) layered structur

20、e. 2.12 solder bump: A discrete amount of solder, attached to the die external metallurgy, that is intended to form an interconnection to a substrate. 2.13 solder pull fracture: A fracture within the bulk of the solder bump column. 2.14 solder void: A cavity within the solder joint that exposes devi

21、ce or the substrate metallurgy. 2.15 stud: The tool that is attached to the backside of the flip chip die to perform tensile pull test. 2.16 substrate: The supporting material upon which one or more semiconductor die are attached. 2.17 substrate fracture: A failure found during tensile pull of flip

22、chip solder joints, where the substrate is fractured and damaged before all the solder bumps are separated. 2.18 tool failure: A failure of stud, fixture, or other mechanical apparatus that prevents the execution of a tensile pull on the die. 2.19 under-bump metallurgy (UBM): The metal layers locate

23、d between the solder bump and the die. 2.20 underfill: The adhesive material applied between the solder bump side of the flip chip die and the substrate. JEDEC Standard No. 22-B109B Page 3 Test Method B109B (Revision of Test Method B109A) 3 Apparatus 3.1 Tool The apparatus for this test shall be equ

24、ipment capable for applying the specified stress as needed to pull the die from the substrate. 3.2 Calibrated measurement A calibrated measurement and indication of the applied stress in millinewtons (mN) or grams-force (gf), where 1 gf = 9.80665 mN (exactly), shall be provided by equipment capable

25、of measuring stresses up to twice the specified minimum-limit value, with an accuracy of 5%, 2.45 mN or 0.25 gf, whichever is the wider tolerance. The use of gf or mN must, of course, agree with the unit used to express the base dimension. This value is based on the number of solder bumps on the die

26、. 4 Procedure 4.1 Device under test preparation This die shall already have been joined to the substrate by way of solder bump reflow operation. There should be no underfill applied on any die on which the flip chip tensile pull test method is being performed. Prior to attaching the stud, the die an

27、d the bonding face of the stud shall be prepared and handled, as needed, to obtain sufficient adhesive bond strength between the stud and the backside of the die so that the tensile pull test can be performed. Appropriate controls and sampling shall be in place to ensure sufficient number solder bum

28、p devices are pulled, in a range that is statistically valid for the quantity of parts being verified. 4.2 Stud attach to die Without disrupting the mechanical integrity of the solder bump interconnections, a stud shall be attached to the backside of the flip chip die with hard setting adhesive glue

29、 capable of sufficient tensile strength to pull the die from the substrate without failing in the adhesive joint. The size of the stud should be properly chosen to avoid instability during the pulling operation. The stud should be no larger than twice the die area. Care should be taken to ensure tha

30、t the adhesive between the stud and the die does not overflow and make contact with the package substrate. A thin, even layer of the bonding adhesive should be applied to the bonding face of the stud, ensuring that the entire bonding face is covered with adhesive. The stud should then be attached to

31、 the backside of the die that is to be tensile pulled. The adhesive should be fully set or cured prior to the tensile pull test procedure being performed. The adhesive selected should not require excessive heat or cure duration since this could effect joint intermetallics/ failure modes. JEDEC Stand

32、ard No. 22-B109B Page 4 Test Method B109B (Revision of Test Method B109A) 4 Procedure (contd) 4.3 Tool setup The substrate with its flip chip joined die shall be held securely in place perpendicular (5) to the direction of the crosshead movement. This is to prevent significant side loading on the so

33、lder bumps. A fixture or method designed to hold the substrate flat and prevent flexure of the substrate during the tensile pull in this manner is needed. 4.4 Tensile pull The die shall be pulled from the substrate. The crosshead speed used for the test should be consistent with the properties of th

34、e solder joints and substrate materials under test. It also needs to be consistent if data comparison is expected. The speed used should be documented. The rate shall not be so high as to induce spurious failure modes. Pull on the stud until the flip chip die is separated from the substrate. It shou

35、ld be noted that the load cell must be capable of handling the load applied during the tensile pull operation. For each flip chip die, record the force at time of failure, and the failure mode of each solder bump in the sample. 5 Inspection criteria a) Nonwet solder bumps, intermetallic fractures, s

36、older pull fractures, delamination, solder voids, die and substrate fracture inspection is performed at 30X magnification and verified at 100X magnification. b) Depending on inspection requirements, other metrologies such as SEM (Scanning Electron Microscope) may be utilized for increased accuracy a

37、nd resolution. c) If any tool failure is observed, root cause is to be identified and recorded. JEDEC Standard No. 22-B109B Page 5 Test Method B109B (Revision of Test Method B109A) 6 Failure criteria 6.1 Modes Failure criteria include, but are not limited to: non-wet solder bumps solder voids solder

38、 pull fracture intermetallic fracture mode die fracture delamination planar fracture die pad fracture passivation to UBM fracture NOTE Failure mode occurrence and type may be affected by differences in the design features (size, pitch, via, etc.) and materials (solder joint, flux, etc.) 6.2 Criteria

39、 determination Upon completion of tensile testing, the solder bumps, on the die and substrate, are inspected and the results recorded for the failure criteria. The allowable level of each of the failure modes and the minimum tensile stress (force per bump/area of pad) needs to be determined as part

40、of the procurement documents for lot acceptance. As such, each solder bump needs to be classified as to displaying a single discrete failure mode. It should be noted that tool failure, substrate fracture and die fracture should not be considered as test failures, but must be recorded. 6.3 Cautions I

41、t should be noted that modes, such as, tool failure, substrate fracture, and die fracture probably affect 100% of the solder bumps on that specific flip chip die. With these modes, the tensile load will be variable and non-uniform in application. Thus the results are not consistent with the norm. Th

42、ough die fracture, substrate fracture, and tool failure are not considered test failures, they should be recorded in the test result information for record completeness. 6.4 Failure mode recording Failure modes of the solder bumps are to be recorded as number of occurrences per device basis, and wil

43、l include each of: device fracture, substrate fracture, delamination, solder void, intermetallic fracture, non-wet, and tool failure. In addition, the ultimate total tensile loading and the calculated average tensile strength which is: (total tensile loading/number of solder bumps)/ area of pad. NOT

44、E The smaller of device or substrate pad areas should be used. The ultimate total tensile loading and calculated average tensile strength and the summary statistics of all failure modes for the devices in the sample will also be recorded. JEDEC Standard No. 22-B109B Page 6 Test Method B109B (Revisio

45、n of Test Method B109A) 7 Summary The following details shall be specified in the applicable procurement documents: a) Solder bump area at each of die and substrate interconnections b) Number of solder bumps c) Sample sizes: Number of flip chip die to be pulled, number of bumps per device. d) Allowa

46、ble defect levels for each flip chip solder tensile pull failure mode. e) Required tensile stress per solder bump. f) Crosshead speed used for tensile pull. g) Substrate material JEDEC Standard No. 22-B109B Page 7 Test Method B109B (Revision of Test Method B109A) Annex A (informative) Differences be

47、tween JESD22-B109B and JESD22-B109A The following list briefly describes most of the changes made to the entries that appear in this publication, JESD22-B109B, compared to its predecessor, JESD22-B109A (January 2009). If the change to a concept involves any words added or deleted, it is included. Pu

48、nctuation changes may not be included. Clause Term and description of change Foreword Clarification 1 Expanding NOTE in Scope for test method application 4.4 Expanding Tensile Pull as it serves both solder joint and substrate evaluation 5 Clarification in Inspection Criteria 6.1 Adding NOTE to Failu

49、re Modes A.1 Differences between JESD22-B109A and JESD22-B109 (June 2002) Clause Term and description of change 1 Added reference to solder type and a note 2 Added new definitions 2,5, 2.10, 2.11 and 2.19 6.1 Added last three modes 6.3 Changed device to die for document consistency JEDEC Standard No. 22-B109B Page 8 Test Method B109B (Revision of Test Method B109A) Standard Improvement Form JEDEC JESD22-B109B The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard.