JEDEC JEP69-B-1973 Preferred Lead Configurations for Field-Effect Transistors《场效应管用优先引脚外形》.pdf

《JEDEC JEP69-B-1973 Preferred Lead Configurations for Field-Effect Transistors《场效应管用优先引脚外形》.pdf》由会员分享，可在线阅读，更多相关《JEDEC JEP69-B-1973 Preferred Lead Configurations for Field-Effect Transistors《场效应管用优先引脚外形》.pdf（7页珍藏版）》请在麦多课文档分享上搜索。

1、EIA JEPb9-B 73 m 3234600 t November: . - 1973 PREFERRED LEAD CONFIGURATIONS FOR FIELD = EFFECT ?*RANSISTORS PRICE $1.00 JEDEC Solid State Products Council JEDEC- PUBLICATION NO. 69 _. - EIA JEPbS-B 73 3234b00 0003373 T Published by ELECTRONIC INDUSTRIES ASSOCIATION Engineering Department 2081 Eye St

2、reet, N.W., Washington, D. C. 20006 EIA JEPb-B 73 3234600 0003374 L JEDEC PUBLICATION NO. 69B PREFERRED LEAD CONFIGURATIONS FOR FIELD-EFFECT TRANSISTORS CONTENTS Triode or Triode-Connected FETs Quadruple-Triode Junction FETs Four-Lead FETS With Two Serially Arranged Gates Triode or Triode-Connected

3、FET Differential Amplifiers Page 1 2 3 4 PREFACE The material contained in this publication was formulated under the cognizance of the JC-24 Committee on Low Power Transistors, This publication supersedes JEDEC Publications 63 and 69. o b - -e EIA JEPb9-B 73 m 3234b00 0003335 3 m PREPERRED LEAD CONF

4、IGURATION FOR TRIODE OR TRIODE-CONNECTED FIELD-EFFECT TRANSISTORS The preferred lead arrangements are shown below for triode field- effect transistors and for field-effect transistors intended for triode connection even though the substrate is brought out inde? pendent of the source, gate, or drain.

5、 This standard applies for circular lead orientations Buch as for TO+, TO-12, TO-18, TO-72 etc Bottom View 1. For depletion types: P-Channel N -Channe 1 Drain, (4) Gate, (4) 2- For enhancement types: Either polarity (i) Drain, (2) Gate, (3) , (4) Source 3. For either type and either polarity: When i

6、t is desired to separate the drain and gate, the following configuration is preferred: (i) Drain, (2) Source, (3) Gate, (4) . In any of the above configurations, the bulk substrate and/or case may be connected to an of the four terminals. The terminal shown with the blank ( or may be omitted. 7 may

7、be used for the case and/or substrate -1- 1 . , EIA JEPbS-B 73 m 3234b00 000337b 5 m PREFERRBD LEAD CONFIGURATION FOR QUADRUPLE-TRIODE JUNCTION FIELD-EFFECT TRANSISOTRS The preferred lead arrangearant for quadruple triodo juiictim fi*ld-effect transietore ir shown belaw. Thie rtandard applieo for pa

8、rptrerol lead packcigeo auch TO-84, T8-81, T0186, 70187 01: TQ48, 1 2 3 4. 5 6 7 To184 Thni TO-86 14 13 12 TOP 11 VZW 10 9 8 a .14 2 13 3 12 4-1 P9 i I 18 7 I. T-87 Thru TO-88 1. Gate 3, Drain 13, Source 14. Gate 12, Drein 4, N.C. or omitted 11. N.C, or ooritted 6. Source Triode 2 9. Source Trid. 1

9、I 8. Cate 5. Drain 7, Cat I 10. Drain -2- - EIA JEPb9-B 73 M 3234b00 0003377 7 M - PREFERRED LEAD CONFIGURATIONS FOR TRIODE OR TRIODE-CONNECTED FIELD-EFFECT DIFFERENTIAL AMPLIFIERS The preferred lead arr$gements for differential amplifiers are shown below for triode field-effect transistors and for

10、field-effect transistors intended for triode connection even though the substrate is brought out independent of the source, gate, or drain. circular lead orientations such as TO-70, TO-71, TO-75, TO-77, TO-78, TO-79, TO-80, etc. This standard applies for 5 Bottom View (1) 1 Source 1 2 Drain 1 3 Gate

11、 1 5 Source 2 6 Drain 2 7 Gate 2 4 8 When it is desired to separate the drain and gate, the following configurations are preferred. (W 1 Drain 1 2 Source 1 3 Gate 1 4 5 Drain 2 6 Source 2 7 Gate 2 8 (III) . 1 Drain 1 5 Gate 2 2 Source 1. 6 Source 2 3 Gate 1 7 Drain 2 4 8 The terminals shown with the

12、 blanks ( ) may be used for the case and/or substrate or may be omitted. When applying this standard to six-lead packages such as TO-75, substitute terminals 4, 5, and 6 for 5, 6, and 7, respectively, in the above configurations. -3- EIA JEPb9-B 73 m 323VbOO O003378 9 m PREFERED LEAD CONFIGUMTION FO

13、R FOUR-LEAD FIELD-EFFECT i1WSISTOFS WITH TWO SERIALLY ARRANGED GATES The preerred lead arrangement shown below is for field-effect transistors . having a source, a signal gate, a shield gate, and 2 drain. This standafd applies for circular lead orientations such as TO-12, TO-17, TO-33, TO-72, TO-104, TO-105, TO-106, etc. 2 1 4 Bottom View Lead - 1 2 3 4 Element Drain Shield gate (gate no. 2) Signal gata (gate no. 1) a Source. and bulk (substrate) -4- .