JEDEC JEP123-1995 Guideline for Measurement of Electronic Package Inductance and Capacitance Model Parameters《电子包装感应系数和电容模式参数测量指南》.pdf

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1、EIA JEPL23 95 EX 3234600 0564151 4TT I W EINJEDEC PUBLICATION Guideline for Measurement of Electronic Package Inductance and Capacitance Model Parameters EIAlJEP123 OCTOBER 1995 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT NOTICE EWJEDEC Standards and Publications contain material that h

2、as been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. EWJEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purch

3、ases, facilitating interchangeabiliy and improvement of products, and assisting the purchaser is selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or

4、 selling products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members, whether the standard is to be used either domestically or internationally. EWJEDEC Standards and Publications are adopted without regard to whet

5、her their adoption may involve patents or articles, materials, or processes. By such action, EWJEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the EWJEDEC Standards or Publications. The information included in EWJEDEC Standards

6、and Publications represents a sound approach to product specification and application, principally fiom the solid state device manufacturer viewpoint. Within the EWJEDEC organization there are procedures whereby an EWJEDEC Standard or Publication may be further processed and ultimately becomes an AN

7、SEIA Standard. Inquiries, comments, and suggestions relative to the content of this EWJEDEC Standard or Publication should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2500 Wilson Boulevard, Arlington, VA 2220 1. Published by OELECTRONIC INDUSTRIES ASSOCIATION 1995 Engineering

8、Department 2500 Wilson Boulevard Arlington, VA 2220 1 “Copyright“ does not apply to JEDEC member companies as they are free to duplicate this document in accordance with the latest revision of the JEDEC Publication 2 1 “Manual of Organization and Procedure“. PRICE: Please refer to the current Catalo

9、g of EIA, JEDEC, and TIA STANDARDS and ENGINEERING PUBLICATIONS or call Global Engineering Documents, USA and Canada (1-800-854-71 79) International (303-397-7956) Printed in U.S.A. All rights reserved EIA JEPL23 95 3234LOO 0564154 LO9 EINJEDEC PUBLICATION No. 1 23 GUIDELINE FOR MEASUREMENT OF ELECT

10、RONIC PACKAGE INDUCTANCE AND CAPACITANCE MODEL PARAMETERS CONTENTS Page 1 Scope 1 2 Introduction 3 Definitions 4 Standard test environment 4.1 General considerations 4.2 Standard test environment implementation 4.3 Standard test environment reporting 5 The measuring instrument 5.1 Instrumentation 5.

11、2 Reporting 6 Calibration 6.1 Reporting 7 Measurement frequency range 7.1 Reporting 2 2 7 7 7 7 7 7 8 8 Test apparatus and procedure for measuring lead inductance 8 8.1 Summary of the method 8 8.2 Test apparatus 8 8.3 Test procedure 9 8.4 Alternative measurement arrangements 10 8.5 Reporting 12 9 Pr

12、ocedure for measuring lead to lead mutual inductance 9.1 Summary of the method 9.2 Test apparatus 9.3 Test procedure 9.4 Reporting 12 12 12 12 13 -1- EIA JEPL23 95 El 3234600 0564355 OY5 EH EIMJEDEC PUBLICATION No. 123 GUIDELINE FOR MEASUREMENT OF ELECTRONIC PACKAGE INDUCTANCE AND CAPACITANCE MODEL

13、PARAMETERS CONTENTS (continued) Page 10 Procedure for measuring lead to lead capacitance 1 O. 1 Summary of the method 10.2 Test apparatus 10.3 Test procedure 10.4 Reporting 11 Procedure for measuring lead to ground capacitance 1 1.1 Summary of the method 11.2 Test apparatus 11.3 Test procedure 1 1.4

14、 Alternative measurement arrangements 1 1.5 Reporting 12 Measurement repeatability 12.1 Reporting 13 Additional, optional information to report 14 References 15 Glossary Annexes A Comments on preferred instrumentation for model parameter measurement B Range of validity of “single lump“ parameter mod

15、els 13 14 14 14 14 14 14 15 15 15 16 16 17 17 17 18 19 20 -11- EIA JEPL23 95 E2 3234600 05L41;5L TBL EIMJEDEC PUBLICATION No. 123 Page 1 GUIDELINE FOR MEASUREMENT OF ELECTRONIC PACKAGE INDUCTANCE AND CAPACITANCE MODEL PARAMETERS (From JEDEC Council Ballot JCB-95- 1 O formulated under the cognizance

16、of JC-15 Committee on Electrical and Thermal Characterization Techniques for Electronic Packages and Interconnects) 1 Scope This measurement guideline is intended to describe the way to establish and prescribe the way to report the conditions in measurements of electrical parameters of individual le

17、ads in semiconductor packages, so that the results are reproducible from site to site. This document describes the “standard test environment“, a set of conditions semiconductor package test fixtures must meet so that they emulate the application environment for the semiconductor device. The standar

18、d methodology is described for deriving lumped model inductance, mutual inductance, capacitance and lead to lead capacitance for semiconductor package leads. This guideline pertains to packages in which lead-to-lead spacing is relatively small as compared to lead-to-ground-plane spacing, as is the c

19、ase in packages with leadfiames, TAB packages and some ball grid array packages. This guideline does not attempt to cover semiconductor packages that contain internal power and ground planes, such as often found in ceramic multilayer packages. This guideline also does not deal with aspects related t

20、o measurement of internal distribution of inductances and capacitances in package leads; it only deals with methodology to measure integral parameter values. The methodology described in this document is restricted to lossless leads, where the assumption is that the energy loss in a lead caused by r

21、adiation ohrnic resistance is negligible. The measurement instrumentation is described in generic form, to enable wider range of instruments to be used with this guideline. Several test procedures are suggested outside the standard methodology, where somewhat lower accuracy is obtained in return for

22、 a much simplified measuring procedure. In conjunction with description of test environment, instrumentation, and measurement procedures, this measurement guideline prescribes the reporting of factors relevant in model parameter measurement, necessary to reproduce the measurement results fiom site t

23、o site. EIA JEPL23 95 E3 3234600 05L4L57 918 EINJEDEC PUBLICATION No. 123 Page 2 2 Introduction The characterization of model parameters for semiconductor package leads has been notorious for the lack of repeatability of modeling and of testing between sites. This lack of repeatability has been caus

24、ed less by inaccuracy of basic test instrumentation, but more by lack of uniform conditions in test fixtures and by the diversity of methods applied. Thus, the intent for test methodology prescribed by this guideline is to ensure the reproducibility of uniform test conditions to be used at various t

25、est sites. As test conditions influence electrical parameter values, they must, to a large extent, emulate the application environment in which semiconductor devices are ultimately used. 3 Definitions No new definitions are given in this document. 4 Standard test environment 4.1 General consideratio

26、ns The values of all electrical parameters characterized by procedures described in this document depend on the electrical environment surrounding the package. This environment will typically change from application to application. This document will describe standard test environment for measuremen

27、t of single lump electrical parameters, a configuration of the test apparatus which most closely approximates the typical electrical environment in existence at the time this document was written. Specification of value of an electrical parameter will imply the assumption that the value in question

28、was derived with the package immersed in the standard test environment. There could be circumstance when it is desirable to derive single lump electrical parameters in environments other than standard, such as in cases when a users electrical environment is atypical and parameter values are desired

29、in such environment. In such exceptional cases, specification of parameters values must be accompanied with the description of electrical environment in detail sufficient to reproduce parameter values to desired accuracy. EIA JEP123 95 El 3234600 0.564158 854 EWJEDEC PUBLICATION No. 123 Page 3 4.2 S

30、tandard test environment implementation An instance of semiconductor package standard test environment is illustrated in figure 1A. The standard test environment comprises the package under test, positioned above a conductive metal plane (ground plane), so that the distance between the body of the p

31、ackage and the ground plane is the same as the distance between the package and the ground plane in a circuitboard this package would be mounted on in an application. Should the final application require a layer of dielectric material positioned between the ground plane and the package, equivalent d

32、ielectric material should be deployed in the test apparatus to reproduce such environment. Package leads that need to be connected to ground during the test are to contact the ground plane. There should be provisions to isolate leads from the ground plane either by virtue of depressions in the surfa

33、ce of the ground plane or by virtue of separation with a dielectric layer. The test signals are brought to the contact electrodes using controlled impedance transmission lines with constant characteristic impedance. A number of alternative ways to accomplish this is illustrated in figure 1B and figu

34、re 1C. The ground plane should be made from nonferromagnetic metal, such as brass or copper, sufficiently thick to overcome skin effect manifestations at frequencies of test signals used in the measurement process. For a lead over a ground plane, the measured inductance will increase when the skin d

35、epth exceeds the thickness of the metal comprising the ground plane. The skin depth is given by 1 6= WG where f is the frequency at which the skin depth is 6, p is the magnetic permeability and u is the conductivity of the ground plane metal. In case of copper, the skin depth will be 8.3 mm at 60 Hz

36、, and 8.3 pm (or 0.00033 inch) at 60 Mhz. This indicates that ground planes implemented in conventional circuitboard technology will provide consistent measurements for frequencies of test signals exceeding 50 Mhz. Outside the ground plane, there should be no conductive or ferromagnetic objects with

37、in the distance where they could significantly influence the results of measurements. The proximity of an electrically conductive plane (ground plane) wili have significant influence on model parameter values for leads in some packages. The intent is for the standard test environment to facilitate g

38、eneration of electrical model values which will faithfully simulate a packaged semiconductor device in an application. A typical application will have a conductive plane either at the surface the device is mounted on or within 0.2 to 0.5 mm within such surface. EIA JEPL23 95 El 3234600 0564359 790 E

39、INJEDEC PUBLICATION No. 123 Page 4 4.3 Standard test environment reporting The standard test environment parameters to be reported together with measurement results are illustrated in figure 1D: - Ground plane separation: the distance between the ground plane and the plane defined by the bottom side

40、 of the package body. - The thickness and composition of the ground plane. - The thickness and composition of the dielectric layer covering the ground plane. - The nature of contact pads bringing test signals to signal leads of the device under test. CONTROLLED IMPEDANCE TRANSMISSION LINE TO MEASURI

41、NG INSTRUMENT PACKAGE UNDER TEST CONDUCTOR MATERIAL LEAD CONTACT LEAD LEAD ISOLATED FROM GROUND PLANE USING DIELECTRIC LAYER LEAD ISOLATED FROM GROUND PLANE USING DEPRESSION Figure 1A - One instance of standard test environment for measuring semiconductor package electrical model parameters EIA JEPL

42、23 75 3234600 0564LLO 402 EWJEDEC PUBLICATION No. 123 Page 5 MICROSTRIP LEAD CONTACT ELECTRODE TRANSMISSION LINE PACKAGE UNDER TEST J OUND PLANE 7 GROUND LEAD CONNECTION COAXIAL PROBE GROUND PLANE GROUND CONNECTION MICROWAVE PROBE GROUND CONNECTION Figure 1B - Alternative ways to bring test signals

43、to package leads with controlled impedance transmission lines. Test signals can also be applied to leads from the inside of the package, if access can be made there 4. A standard test environment future can be fabricated as well using printed circuitboard technology. EIA JEPL23 95 3234LOO 0564LbL 3Y

44、 EINJEDEC PUBLICATION No. 123 Page 6 CONTROLLED IMPEDANCE PROBE BALL CONTACT ELECTRODE GROUND PLANE / COUiER BAU INTERCONNECT LEAD BGA PACKAGE (TURNED UPSIDE-DOWN) UNDER TEST Figure 1C - Bringing test signals to packages with area-array leads, such as in ball grid array packages. TRANSMISSION LINE C

45、ONTACT PAD (THICKNESS. SIZE) PACKAGE UNDER TEST J I E GROUND PUNE I DIELECTRIC LAYER THICKNESS Figure 1D - Parameters characterizing standard test environment EIA JEPL23 75 rl 3234600 0564362 285 E3 EINJEDEC PUBLICATION No. 123 Page 7 5 The measuring instrument 5.1 Instrumentation The instrumentatio

46、n for measuring inductance and capacitance values can be an LC meter or an impedance analyzer i, a TDR (Time Domain Reflectometry) based analyzer 2,3 or a vector network based analyzer 4. 5.2 Reporting Model values derived from measurements should be accompanied by the information on: - Instrument t

47、ype (e.g., LC-meter, TDR instrument, VNA, etc.) - The model number and the name of the manufacturer. 6 Calibration The calibration should be performed at the point (plane) from which the signal is launched into the lead under test. This means that calibration standards, such as “open“, “short“, “loa

48、d“, and samples with known parameter values are attached at the point where the lead under test will be connected. If calibration is performed at some other point in the test signal path, the effects of the lead between the calibration point and the device under test must be accounted for in derivin

49、g model parameter values. 6.1 Reporting - Calibration at the point of signal launching into the lead under test is assumed and only variances of this condition need to be reported. - Optionally, details on particular standard used for calibration can be reported. 7 Measurement frequency range Some electrical package parameters depend on frequency (such as inductance variations with frequency caused by skin effect in the lead), so parameter values can be measured asymptotically, in the low frequency limit 4,5. When using an LC meter, the lowest test signal freque