DLA SMD-5962-98619-1999 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS OCTAL DUAL SUPPLY CONFIGURABLE VOLTAGE INTERFACE TRANSCEIVER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON《微型电路 数字型 低压CM.pdf

《DLA SMD-5962-98619-1999 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS OCTAL DUAL SUPPLY CONFIGURABLE VOLTAGE INTERFACE TRANSCEIVER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON《微型电路 数字型 低压CM.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-98619-1999 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS OCTAL DUAL SUPPLY CONFIGURABLE VOLTAGE INTERFACE TRANSCEIVER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON《微型电路 数字型 低压CM.pdf（20页珍藏版）》请在麦多课文档分享上搜索。

1、REVISIONSLTR DESCRIPTION DATE (YR -MO -DA) APPROVEDREVSHEETREVSHEET 15 16 17 18 19REV STATUS REVOF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14PMIC N/A PREPARED BY Joseph A. KerbyDEFENSE SUPPLY CENTER COLUMBUSSTANDARDMICROCIRCUITDRAWINGCHECKED BY Charles F. Saffle, Jr.COLUMBUS, OHIO 43216THIS DRAWI

2、NG IS AVAILABLEFOR USE BY ALLDEPARTMENTSAPPROVED BYMonica L. Poelking MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS,OCTAL DUAL SUPPLY CONFIGURABLE VOLTAGEAND AGENCIES OF THEDEPARTMENT OF DEFENSE DRAWING APPROVAL DATE99-02-01INTERFACE TRANSCEIVER WITH THREE-STATEOUTPUTS, MONOLITHIC SILICONAMSC N/A REVISION

3、 LEVEL SIZEA CAGE CODE 67268 5962-98619SHEET 1 OF 19DSCC FORM 2233APR 97 5962 -E115-99DISTRIBUTION STATEMENT A . Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA

4、5962-98619DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL SHEET 2DSC C FORM 2234APR 971. SCOPE1.1 Scope . This drawing documents two product assurance class levels consisting of high reliability (device classes Q andM) and space application (device class V). A choice of case o

5、utlines and lead finishes are available and are reflected in the Partor Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.1.2 PIN . The PIN is as shown in the following example:5962 - 98619 01 Q K XFederal RHA Device Device Case

6、Lead stock class designator type class outline finishdesignator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3)/ Drawing number1.2.1 RHA designator . Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and aremarked with the appropriate RHA

7、designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix Aspecified RHA levels and are marked with the appropriate RHA designator. A dash ( -) indicates a non -RHA device.1.2.2 Device type(s) . The device type(s) identify the circuit function as follows:Device type Generic numb

8、er Circuit function01 54LVXC3245 Octal dual supply configurable voltage interfacetransceiver with three-state outputs1.2.3 Device class designator . The device class designator is a single letter identifying the product assurance level asfollows:Device class Device requirements documentationM Vendor

9、 self -certification to the requirements for MIL-STD-883 compliant,non -JAN class level B microcircuits in accordance with MIL-PRF-38535,appendix AQ or V Certification and qualification to MIL-PRF-385351.2.4 Case outline(s) . The case outline(s) are as designated in MIL-STD-1835 and as follows:Outli

10、ne letter Descriptive designator Terminals Package styleK GDFP2-F24 or CDFP3-F24 24 Flat packL GDIP3-T24 or CDIP4-T24 24 Dual-in-line3 CQCC1-N28 28 Square leadless chip carrier 1 /1.2.5 Lead finish . The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, append

11、ixA for device class M.1 / This package is not available from an approved source of supply as of the date of this drawing.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA 5962-98619DEFENSE SUPPLY CENTER COLUMBUSCOLUMB

12、US, OHIO 43216-5000 REVISION LEVEL SHEET 3DSC C FORM 2234APR 971.3 Absolute maximum ratings . 1 / 2 / 3 /Supply voltage range (V CCA , V CCB ) . -0.5 V dc to +7.0 V dcDC input voltage range (V IN ) -0.5 V dc to V CCA + 0.5 V dcDC input / output voltage range, An (V I/O ) -0.5 V dc to V CCA + 0.5 V d

13、cDC input / output voltage range, Bn (V I/O ) -0.5 V dc to V CCB + 0.5 V dcDC input diode current (I IK ) 20 mADC output diode current (I OK ) . 50 mADC output source or sink current (I O ) (per pin) . 50 mADC V CC or GND current . 200 mAMaximum power dissipation (P D ) 500 mWStorage temperature ran

14、ge (T STG ) -65 C to +150 CLead temperature (soldering, 10 seconds) . +300 CThermal resistance, junction-to-case ( JC ) See MIL -STD -1835Junction temperature (T J ) +175 C 4 /1.4 Recommended operating conditions . 2 / 3 / 5 /Supply voltage range (V CCA ) (V CCA V CCB ) . +2.7 V dc to +3.6 V dcSuppl

15、y voltage range (V CCB ) +3.0 V dc to +5.5 V dcInput voltage range (V IN ) . +0.0 V dc to V CCAInput / output voltage range, An (V I/O ) +0.0 V dc to V CCAInput / output voltage range, Bn (V I/O ) +0.0 V dc to V CCBMinimum high level input voltage, An, T/R, OE (V IH ) +2.0 V dcMaximum low level inpu

16、t voltage, An, T/R, OE (V IL ) . +0.8 V dcMinimum high level input voltage, Bn (V IH ):3.0 V V CCB 3.6 V +2.0 V dc3.6 V 1 MHz.b. t r , t f = 3 ns 1.0 ns. For input signal generators incapable of maintaining these values of t r and t f , the 3.0 ns limit may be increased up to 10 ns, as needed, maint

17、aining the 1.0 ns tolerance and guaranteeing the results at3.0 ns 1.0 ns; skew between any two switching input signals ( t sk ): 250ps.FIGURE 4. Ground bounce load circuit and waveforms .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCI

18、RCUIT DRAWINGSIZEA 5962-98619DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL SHEET 14DSC C FORM 2234APR 97An to BnNOTES:1. When measuring t PLH and t PHL : V TEST = open.2. When measuring t PLZ and t PZL : V TEST = 2 x V CCB .3. Wh en measuring t PHZ , t PZH : V TEST = GND.4.

19、The t PZL and t PLZ reference waveform is for the output under test with internal conditions such that the output is at V OLexcept when disabled by the output enable control. The t PZH and t PHZ reference waveform is for the output under test with internal conditions such that the output is at V OH

20、except when disabled by the output enable control.5. C L = 50 pF minimum or equivalent (includes test jig and probe capacitance).6. R L = 500 or equivalent.7. R T = 50 or equivalent.8. Input signal from pulse generator: V IN = 0.0 V to 2.7 V; PRR 10 MHz; t r 3.0 ns; t f 3.0ns; t r and t f shall be m

21、easured from 0.27 V to 2.43 V and from 2.43 V to 0.27 V, respectively; duty cycle = 50 percent.9. Timing parameters shall be tested at a minimum input frequency of 1 Mhz.10. The outputs are measured one at a time with one transition per measurement.FIGURE 5. Switching waveforms and test circuit .Pro

22、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA 5962-98619DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL SHEET 15DSC C FORM 2234APR 97Bn to AnNOTES:1. When m easuring t PLH and t PHL : V TEST = o

23、pen.2. When measuring t PLZ and t PZL : V TEST = 6.0 V.3. When measuring t PHZ , t PZH : V TEST = GND.4. The t PZL and t PLZ reference waveform is for the output under test with internal conditions such that the output is at V OLexcept when disabled by the output enable control. The t PZH and t PHZ

24、reference waveform is for the output under test with internal conditions such that the output is at V OH except when disabled by the output enable control.5. C L = 50 pF minimum or equivalent (includes test jig and probe capacitance).6. R L = 500 or equivalent.7. R T = 50 or equivalent.8. Input sign

25、al from pulse generator: V IN = 0.0 V to V CC ; PRR 10 MHz; t r 3.0 ns; t f 3.0ns; t r and t f shall be measured from 10% of V CC to 90% of V CC and from 90% of V CC to 10% of V CC , respectively; duty cycle = 50 percent.9. Timing parameters shall be tested at a minimum input frequency of 1 Mhz.10.

26、The outputs are measured one at a time with one transition per mea surement.FIGURE 5. Switching waveforms and test circuit - Continued.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA 5962-98619DEFENSE SUPPLY CENTER C

27、OLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL SHEET 16DSC C FORM 2234APR 974. QUALITY ASSURANCE PROVISIONS4.1 Sampling and inspection . For device classes Q and V, sampling and inspection procedures shall be in accordance withMIL-PRF-38535 or as modified in the device manufacturers Quality Managem

28、ent (QM) plan. The modification in the QM planshall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall bein accordance with MIL-PRF-38535, appendix A.4.2 Screening . For device classes Q and V, screening shall be in accordance with

29、 MIL-PRF-38535, and shall be conductedon all devices prior to qualification and technology conformance inspection. For device class M, screening shall be inaccordance with method 5004 of MIL -STD -883, and shall be conducted on all devices prior to quality conformance inspection.4.2.1 Additional cri

30、teria for device class M .a. Burn -in test, method 1015 of MIL -STD -883.(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revisionlevel control and shall be made available to the preparing or acquiring activity upon request. The test circuit s

31、hallspecify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specifiedin test method 1015.(2) T A = +125 C, minimum.b. Interim and final electrical test parameters shall be as specified in table II herein.4.2.2 Additional criteria for device classes Q

32、and V .a. T he burn -in test duration, test condition and test temperature, or approved alternatives shall be as specified in thedevice manufacturers QM plan in accordance with MIL-PRF-38535. The burn -in test circuit shall be maintainedunder document revision level control of the device manufacture

33、rs Technology Review Board (TRB) in accordancewith MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuitshall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specifiedin test method 101

34、5 of MIL-STD-883.b. Interim and final electrical test parameters shall be as specified in table II herein.c. Additional screening for device class V beyond the requirements of device class Q shall be as specified inMIL-PRF-38535, appendix B.4.3 Qualification inspection for device classes Q and V . Q

35、ualification inspection for device classes Q and V shall be inaccordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein forgroups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).4.3.1 Electrostatic discharge sensitivity qualification insp

36、ection . Electrostatic discharge sensitivity (ESDS) testing shall beperformed in accordance with MIL -STD -883, method 3015. ESDS testing shall be measured only for initial qualification andafter process or design changes which may affect ESDS classification.4.4 Conformance inspection . Technology c

37、onformance inspection for classes Q and V shall be in accordance withMIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 ofMIL-PRF-38535 permits alternate in -line control testing. Quality conformance inspection for dev ice class M shall be inac

38、cordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall bethose specified in method 5005 of MIL -STD -883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).Provided by IHSNot for ResaleNo reproduction or networ

39、king permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA 5962-98619DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL SHEET 17DSC C FORM 2234APR 97TABLE II. Electrical test requirements .Test requirements Subgroups(in accordance withMIL-STD-883,method 5005, t

40、able I)Subgroups(in accordance withMIL-PRF-38535, table III)Deviceclass MDeviceclass QDevi ceclass VInterim electricalparameters (see 4.2)- - - - - - 1Final electricalparameters (see 4.2)1 / 1, 2, 3, 7,8, 9, 10, 111 / 1, 2, 3, 7,8, 9, 10, 112 / 1, 2, 3, 7,8, 9, 10, 11Group A testrequirements (see 4.

41、4)1, 2, 3, 4, 7,8, 9, 10, 111, 2, 3, 4, 7,8, 9, 10, 111, 2, 3, 4, 7,8, 9, 10, 11Group C end-point electricalparameters (see 4.4)1, 2, 3 1, 2, 3 1, 2, 3, 7,8,9, 10, 11Group D end-point electricalparameters (see 4.4)1, 2, 3 1, 2, 3 1, 2, 3Group E end-point electricalparameters (see 4.4)1, 7, 9 1, 7, 9

42、 1, 7, 91 / PDA applies to subgroup 1.2 / PDA applies to subgroups 1 and 7.4.4.1 Group A inspectiona. Tests shall be as specified in table II herein.b. For dev ice class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. The testvectors used to verify the tr

43、uth table shall, at a minimum, test all functions of each input and output. All possible inputto output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2, herein. For deviceclasses Q and V, subgroups 7 and 8 shall include verifying the functionality of th

44、e device.c. C IN , C I/O , and C PD shall be measured only for initial qualification and after process or design changes which may affectcapacitance. C IN and C I/O shall be measured between the designated terminal and GND at a frequency of 1 MHz. Thistest may be performed at 10 MHz and guaranteed,

45、if not tested, at 1 MHz. C PD shall be tested in accordance with thelatest revision of JEDEC Standard No. 20 and table I herein. For C IN , C I/O , and C PD , test all applicable pins on fivedevices with zero failures.For C IN and C I/O , a device manufacturer may qualify devices by functional group

46、s. A specific functional group shall becomposed of function types, that by design, will yield the same capacitance values when tested in accordance withtable I, herein. The device manufacturer shall set a functional group limit for the C IN and C I/O tests. The devicemanufacturer may then test one d

47、evice function from a functional group, to the limits and conditions specified herein. All other device functions in that particular functional group shall be guaranteed, if not tested, to the limits andconditions specified in table I, herein. The device manufacturers shall submit to DSCC-VA the dev

48、ice functions listedin each functional group and test results for each device tested.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA 5962-98619DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL SHEET 18DSC C FORM 2234APR 97d. Ground and V C C bounce tests are required for all device classes. These tests shall be performed only for initialqualification, after process or design changes which may affect the performance of the device, and any changes to thetes