DLA SMD-5962-95715-1996 MICROCIRCUIT DIGITAL CMOS CLOCK GENERATOR DRIVER MONOLITHIC SILICON《数字的互补金属氧化物半导体时钟驱动器硅单片电路线型微电路》.pdf

《DLA SMD-5962-95715-1996 MICROCIRCUIT DIGITAL CMOS CLOCK GENERATOR DRIVER MONOLITHIC SILICON《数字的互补金属氧化物半导体时钟驱动器硅单片电路线型微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-95715-1996 MICROCIRCUIT DIGITAL CMOS CLOCK GENERATOR DRIVER MONOLITHIC SILICON《数字的互补金属氧化物半导体时钟驱动器硅单片电路线型微电路》.pdf（17页珍藏版）》请在麦多课文档分享上搜索。

1、REVISIONS LTR DESCRIPTION DATE (YRMO-DA) APPROVED REV I I SIZE A =+Ti- SHEET 5962-9571 5 CAGE CODE 67268 REV STATUS OF SHEETS STANDARD MICROCIRCUIT D RAW1 N G THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC NIA PREPARED BY Thomas M. Hess DEFENSE EL

2、ECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 CHECKED BY Thomas M. Hess APPROVED BY Monica L. Poelking DRAWING APPROVAL DATE 96-01 -1 1 REVISION LEVEL MICROCIRCUIT, DIGITAL, CMOS, CLOCK GENERATOR DRIVER, MONOLITHIC SILICON I SHEET 1 OF 16 DESC FORM 193 JUL 94 5962-E271 -96 DISTRIBUTION STATEMENT A Appr

3、oved for public release, distribution is unlimited Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-1. SCOPE 1.1 -. This drawing forms a part of a one part - one part nunber docunentation system (see 6.6 herein). Two product assurance classes consisti

4、ng of military high reliability (device classes Q and M) and space application (device class V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Nunber (PIN). 1.2.1 of MIL-STD-883, IIProvisions for the use of MIL-STD-883 in conjunction with

5、conpliant non-JAN devices“. available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. Device class M microcircuits represent non-JAN class B microcircuits in accordance with men 1 1.2 M. The PIN shall be as shown in the following exanple: fLtf Federal R HA Device Dev

6、ice Case Lead stock class designator type c 1 ass outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) LU (see 1.2.3) / Drawing nunber Device tvD e o1 Generic number 82C84A/7 Circuit function Latchup resistance CMOS clock generator driver 1.2.3 Device class desiqnato

7、r. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device reauirements documentation M Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 Certification and quali

8、fication to MIL-1-38535 I a or v 1.2.4 Case outiine(s1 . The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Prrtline letter Descri ot 1 v e des ianator Jermi nab - . V CDIP2-118 18 Dual - in- 1 ine package . 1.2.5 Lead finish The lead finish shall be as specified in MIL-STD-8

9、83 (see 3.1 herein) for class M or MIL-1-38535 for classes 0 and V. designation is for use in specifications when lead finishes A, 6, and C are considered acceptable and interchangeable without preference. Finish letter 88X88 shall not be marked on the microcircuit or its packaging. The 5962-9571 5

10、REVISION LEVEL SHEET STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Supply voltage (VCC) - - - - - - - - - - - - - - - - - - - - - - Input or ou

11、tput voltage range - - - - - - - - - - - - - - - - - Storage temperature range (TSTG) - - - - - - - - - - - - - - - - Junction tenperature (TJ) - - - - - - - - - - - - - - - - - - - Maxim package power dissapation at T - - - - Thermal resistance, Junction-to-case overnment soecification. standards.

12、bulletin. and handbook. Unless otherwise specified, the following specification, standards, bulletin, and handbook of the issue listed in that issue of the Department of Defense Index of Specifications and Standards specified in the solicitation, form a part of this drawing to the extent specified h

13、erein. SPECIFICATION MILITARY MIL-1-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS MILITARY MIL-STD-883 - Test Methods and Procedures for Microelectronics. MIL-STD-973 - Configuration Management. MIL-STD-1835 - Microcircuit Case Outlines. BULLETIN MILITARY MIL-BUL-1

14、03 - List of Standardized Military Drawings (SMDIS). HANDBOOK MILITARY MIL-HDBK-780 - Standardized Military Drawings. 2.2 Order of Drecedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. DESC FORM 193A J

15、UL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5762-95715 999999b 0083919 917 SIZE STANDARD A MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL 5962-9571 5 SHEET 4 Provided by IHSNot for ResaleNo repr

16、oduction or networking permitted without license from IHS-,-,-vcc = 4.5 v, IO! = 2.5 mA Pins 2,5,10,12, 6 2 1,2,3 Al l 0.4 vcc = 5.5 v, Vy = VCF Pins 1,3,4,6,7, 1,13, 4 untested pins = VCc or GND o/ Vcc = 5.5 V, VI GND Pins 1,3,4,6,7,!113,14 untested pins = Vcc or CND o/ See 4.4.1 Vcc = Open f = 1 M

17、Hz 4 Al l 15 TABLE I. m. Test Conditions -55.C i TA L +125C unless otherwise specified u Unit Limits .ogical input 1 voltage H I l V VIL V .ogical input 2 voltage teset logical 1 input voltage V vcc = 5.5 v, Pin 11 z/ I 1,2,3 1 All 1 4.7 I VI HR VI LR V leset logical O input voltage leset input hyst

18、ersis VH Vcc = 4.5 V, Vcc = 5.5 V Pin 11 1 1,2,3 I All I0.2Vcc I V lutput high voltage 1 U,-c = 4.5 V, Io Pins 2,5,10,12,!6 5/ = -2.5 mA I 1,2,3 I All IVcc-0.4 1 lutput high voltage VOH2 Vcc = 4.5 V, IOH = -4.0 m4 Pins 8 2 1 1,2,3 1 All /Vcc-O.4 1 v VOL1 V lutput low voltage V lutput low voltage VOL

19、2 IIH I lS0 ligh input leakage current IL .ow input leakage current Jperating power supply current ICCOP VDD = 5.5 V 7J Output open 40 IN See 4.4.1 Vcc = Open f = 1 MHz 10 PF input capacitance Output capacitance PF CWT See footnotes at end of tabLe. I SIZE I STANDARD MICROCIRCUIT DRAWING DEFENSEELEC

20、TRONICSSUPPLYCENTER DAYTON, OHIO 45444 5962-9571 5 I SHEET 5 REVISION LEVEL DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-95715 = 9999996 O083923 575 Test Functional tests Condi ti ons Group A Device Limits Unit -55C

21、s TA s +125C subgroups type Synibol unless otherwise specified u Min Max vcc = 4.5 v 7,8 Al l vcc = 5.5 v vc. = 4.5 v y H/ vcc = 5.5 v dcc = 4.5 v z/ s/ dcc = 5.5 v &-c = 4.5 v 1/ H/ dcc = 5.5 v icc = 4.5 v 3 8/ Jcc = 5.5 v Icc = 4.5 v I/ aJ ICC 5.5 v 9,10,11 9,10,11 9,10,11 9,10,11 9,10,11 20 20 ns

22、 ns - Al l - Al 1 - ALL - ALL - At l RDYl, RDYZ active setup time to CLK ASYNC = H 7DY1, RDYZ active setup time to CLK ASYNC = L IDY1, RDYZ inactive setup time to CLK ASYNC = L tOY1, RDYZ hold to CLK ti ti SYNC setup to CLK - 4SYNC hold to CLK LAYX Al l 9,10,11 - Ell, AEN2 setup to RDYl, RDYZ Al 1 t

23、ii 9,10,11 - 4EN1, AEN2 hold to CLK Icc = 4.5 v 1/ s/ Icc 5.5 v %LAX 9,10,11 Al l - Al l - Al l :SYNC setup to EFI Icc = 4.5 v 3J 8/ icc = 5.5 v 9,10,11 9,10,11 :SYNC hotd to FI t See footnotes at end of table. 5962-95715 REVISION LEVEL SHEET STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY

24、CENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TABLE I. Eiectrical oerformance characteristics - ContinuTl. lest symbo I Conditions Group A Device -55C s TA s +125C subgroups type unless otherwise spec

25、ified i/ TIMING REQUIREMENTS - CONTINUED. tI1HCL VCC = 4.5 I/ H/ e/ 9,10,11 ALL VCC = 5.5 v tEHEL vcc 4.5 v I/ H/ 1p/ 9,10,11 ALL vcc = 5.5 v tELEH vcc = 4.5 v I/ 8/ o/ 9,10,11 ALL vcc = 5.5 v tELEL vcc = 4.5 v z/ s/ 9,10,11 ALI vcc = 5.5 v OLCH VCC = 4-5 V 2 8/ 9,10,11 All vcc = 5.5 v toLC- vcc = 4

26、.5 v 2 s/ 9,10,11 All vcc = 5.5 v vcc = 4.5 v s/ JI-/ 9,10,11 ALL vcc = 5.5 v RES setup to CLK 65 ns 18 ns 18 ns 36 ns 22 ns 35 ns 2.4 25 MHz Externat frequency high time RES hold to CLK :LK cycle period :LK high time ELK low time External frequency low time CLIH VCC 4-5 V U 8/ e/ 9,10,11 ALL 20 ns

27、vcc = 5.5 v tCLCL vcc = 4.5 v s/ l?J 9,10,11 ALL 125 ns vcc = 5.5 v tC“CL vcc = 4-5 v u u/ 9,10,11 All (1/3)tC ns 4.b vcc = 5.5 v CLC CH VCC = 4.5 V 1u 9,10,11 ALL (2/3)t,-kcL ns vcc = 5.5 v EFI period 3SC to CLK high time de 1 ay 3SC to CLK low time de i ay KTAL frequency TIMING RESPONES Limits Uni

28、t Min I Max I See footnotes at end of table. STAN DARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 5962-9571 5 I REVISION LEVEL I SHEET 7 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-957L5

29、9999996 0083923 348 - Continued. TABLE I. 1 Unit Limits Test Symbol Condi ti ons Groy, A Device -55C i TA s +125C subgroups type unless otherwise specified u Min Max TIMING RESPONES - CONTINUED. CLK rise or fall time PCLK high time PCLK low time Ready inactive to CLK Ready active to CLK CLK to reset

30、 delay CLK to PCLK high de l ay CLK to PCLK low delay CSYNC uidth OSC to CLK high delay OCC to CLK low delay See footnotes at end of table. SIZE STANDARD A 5962-9571 5 MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 8 DESC FORM 193A JUL 94 - 9,10,11 9,1

31、0,11 All 10 ns Al 1 tCLCL-ZO ns I tCLIL t vcc = 4.5 v 3/ g/ vcc = 5.5 v tCLPH I 9,10,11 I All ItCLCL-20 vcc = 4.5 v 3/ s/ vcc = 5.5 v I ns Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TABLE IA. Electrical oerformance characteristics - Continued. I

32、/ u 1/ This test is performed as Go/No Go. There are no recorded measurements. All Testing to be performed using worst case test conditions unless otherwise specified. F/C is a strap on option and should be held J 0.8 V or 2 2.2 V. Does not apply to XI or X2 pins. CSYNC pin is tested with VIL = 0.8

33、V. Interchanging force and sense conditions is permitted. 5/ / ASYNC pin includes an internal 17.5 k pull-up resistor. - - - For ASYNC input at GND, ASYNC input leakage = 300 pl nominal A STANDARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 f = 25 MHz may be tested using t

34、he extrapolated value based on measurements at f = 2 MHz and f = 10 MHz. 8/ F = 2.4 Mhz, VIH = 2.6 V, VI switch between 0.4 V and Vcc - 0.k V. LSYNCH pin. e/ 1p/ L1/ Tested using EFI or X1 input pin. 1l/ Tested with EFI input frequency = 4.2 MHz. u/ Applies only to T2 states. w Applies only to T3, T

35、U states. L5/ snd Vcc - 0.4 V. 5.5 V. o/ This parameter is guaranteed but not tested. This parameter is characterizedupon initial design or process :hange which affects this parameter. - = 0.4 V, Vou L 1.5 V, VOL s 1.5 V unless otherwise specified. RES and F/C must VIL s VIL(max) - 0.4 V for Input r

36、ise and fall times are driven at 1 ns/V. Setup and hold necessary only to guarantee recognition at next clock. TELEH and TEHEL are determined by 50 percent points. Input test signal must switch between VIL(Max) - 0.4 V and V (Min) + 0.4 V RES and F/C must switch between 0.4 V Input rise and fall tim

37、es driven at lns/V. VIL1! VIL(Max) - 0.4 V for CSYNCH pin. Vcc = 4.5 V and 5962-95715 REVISION LEVEL SHEET 9 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-FIGURE i. Terminal connections. JUL 94 Provided by IHSNot for ResaleNo

38、reproduction or networking permitted without license from IHS-,-,-SMD-5962-757L5 7999996 008392b 057 RES XI XZ F/C EF 1 CSYNC ROY 1 AEN1 RDYZ - AEN2 ASYNC 11 4 RESET osc PCLK CLK READY FIGURE 2. Block diasram. STANDARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 IAl I 5962

39、-95715 REVISION LEVEL I SHEET1l I 1 1 DECC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-957L5 U 9999996 O083927 T93 SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 5962-9571 5 REVISI

40、ON LEVEL SHEET 12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-%5715 9999996 0083928 92T 4. QUALITY ASSURANCE PROVISIONS 4.1 SanuLina and insmct ia. For device class M, sampling and inspection procedures shall be in accordance with MIL-CT

41、D-883 (see 3.1 herein). For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-1-38535 or as modified in the device manufacturers Quality Managenient (W) plan. plan shall not effect the form, fit, or function as described herein. The modification in the Pn 4.2

42、 Screen inq. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. For device ciasses Q and V, screening shall be in accordance with MIL-1-38535, and shall be conducted on all devices prior

43、 to qualification and technology conformance inspect i on. 4.2.1 Additional criteria for device class y. a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, 6, C or D. The test circuit shall be maintained by the manufacturer under docunent revision levei control and shall be made avai

44、lable to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (2) TA = +125C, minim. b. Interim and final electrical test parameters shall be as

45、 specified in table IIA herein. 4.2.2 Additional criteria for device classes Q and V. a. lhe burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturers OM plan in accordance with MIL-1-38535. The burn-in test circuit shall b

46、e maintained under docunent revision level control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-1-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipati

47、on, as applicable, accordance with the intent specified in test method 1015. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as spec appendix B of MIL-1-38535, or

48、as modified in the device manufacturers approved Quality Management 4.3 Qualification insDection for device classes Q and V. Qualification inspection for device classes Q and V shall Inspections to be performed shall be those specified in MIL-1-38535 and herein for be in accordance with MIL-1-38535. groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 . . Quality conformance inspection for device class M shall be in accordance with 4IL-STD-883 (see 3.1 herein) and as specified herein. Inspections to be performed for device class M shall be those specified in method 500