DLA SMD-5962-85102 REV F-2011 MICROCIRCUITS MEMORY DIGITAL CMOS 8K x 8 UV ERASABLE PROM MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED C Added CAGE number 1FN41 and 34335 to the drawing as approved sources of supply. Added vendor CAGE number 18324 to device types 01ZX, 02ZX, and 03ZX, with changes to margin test methods A and B. Added device type 07 to the drawing for vendor CAGE

2、number 65579 with changes to table I. Deleted figure 5 and table III. Also, deleted program method column from 6.6. Editorial changes throughout. 89-10-30 M. A. Frye D Added provisions for the addition of QD certified parts to drawing. Updated boilerplate. Added CAGE OC7V7 as supplier. - glg 00-06-2

3、3 Raymond Monnin E Corrected marking paragraph 3.5, updated boilerplate paragraphs. ksr 05-03-28 Raymond Monnin F Boilerplate update, part of 5 year review. ksr 11-03-03 Charles F. Saffle THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. CURRENT CAGE CODE 67268 REV SHEET REV SHEET REV STATU

4、S REV F F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Sandra Rooney DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY D A DiCenzo COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF

5、 THE DEPARTMENT OF DEFENSE APPROVED BY N A. Hauck MICROCIRCUITS, MEMORY, DIGITAL, CMOS, 8K x 8 UV ERASABLE PROM, MONOLITHIC SILICON DRAWING APPROVAL DATE 10 January 1986 AMSC N/A REVISION LEVEL F SIZE A CAGE CODE 14933 85102 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E168-11 Provided by IHSNot for Res

6、aleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85102 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant,

7、non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN shall be as shown in the following example: 85102 01 Y X | | | | | | | | | | | | Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1

8、.2.3) 1.2.1 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit Access time 01 27C64-25 8K x 8-bit CMOS UVEPROM 250 ns 02 27C64-35 8K x 8-bit CMOS UVEPROM 350 ns 03 27C64-20 8K x 8-bit CMOS UVEPROM 200 ns 04 27C64-90 8K x 8-bit CMOS U

9、VEPROM 90 ns 05 27C64-12 8K x 8-bit CMOS UVEPROM 120 ns 06 27C64-15 8K x 8-bit CMOS UVEPROM 150 ns 07 57C64-70 8K x 8-bit CMOS UVEPROM 70 ns 1.2.2 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835, and as follows: Outline letter Descriptive designator Terminals Package styl

10、e 1/ Y GDIP1-T28 or CDIP2-T28 28 dual-in-line package Z CQCC1-N32 32 rectangular chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Storage temperature range . -65C to +150C All input or output voltages with respect to

11、ground . -2.0 V dc to +7.0 V dc 2/ Voltage on A9with respect to ground -2.0 V dc to +13.5 V dc 2/ VPPsupply voltage with respect to ground during programming . -2.0 V dc to +14.0 V dc 2/ Maximum power dissipation (PD): 3/ Device types 01 and 03 170 mW Device type 02 140 mW Device types 04, 05, 06, a

12、nd 07 550 mW Lead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC): Cases Y and Z See MIL-STD-1835 Junction temperature (TJ) +150C Data Retention 10 years, minimum 1/ Lid shall be transparent to permit ultraviolet light erasure. 2/ Minimum dc input voltage is -0.

13、5 V dc, during transitions, the inputs may undershoot to -2.0 V dc for periods less than 20 ns. 3/ Must withstand the added PDdue to short-circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 8

14、5102 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Case operating temperature range (TC) . -55C to +125C Input low voltage +10% supply (VIL) . -0.5 V dc to +0.8 V dc Input high voltage +10% supply (VIH) . 2.0 V dc

15、 to VCC+0.5 V dc Supply voltage range (VCC) 4.5 V dc to 5.5 V dc 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of

16、 these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Ele

17、ctronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order

18、 Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and reg

19、ulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualifie

20、d Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-

21、38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow opt

22、ion is used. This drawing has been modified to allow the manufacturer to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535 or alternative approved by the Qualifying Activity. 3.2 Design, construction, and physical dimensions. The design, construction, and physical

23、dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Truth tables. The truth table shall be as specified on figure 2. 3.2.2.1 Programmed devices. The requirements for supplying programm

24、ed devices are not a part of this drawing. 3.2.3 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85102 DLA LAND AND MARITIME COLUMBUS, OHI

25、O 43218-3990 REVISION LEVEL F SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. | | | | | | Test |Symbol | Conditions | Group A |Device | Limits | | | -55C TC +125C |subgroups | type | |Unit | | 4.5 V VCC 5.5 V | | | Min | Max | | | unless otherwise specified | | | | | |

26、 | | | | | | Input load current |ILI|VIN= 5.5 V or GND 1/ | 1, 2, 3 | All |-10 | 10 | A | | | | | | | | | | | | | Output leakage current |ILO|VOUT= 5.5 V or GND | 1, 2, 3 | All |-10 | 10 | A | | | | | | | | | | | 04 | | 75 | Operating current, TTL |ICC|CE = OE = VIL| |01, 03 | | 30 | mA inputs 2/ |T

27、TL |VPP= VCC| 1, 2, 3 | 02 | | 25 | | |00-07= 0 mA | | 05 | | 65 | | |f = 5 MHz min | | 06 | | 60 | | | | | 07 | | 65 | | | | | 04 | | 60 | Operating current 3/ |ICC|CE = OE = VIL| 1, 2, 3 |01,02, | | 10 | mA |CMOS |VPP= VCC| | 03 | | | | |00-07= 0 mA | | 05 | | 55 | | |f = 5 MHz min | | 06 | | 50 |

28、 | | | | 07 | | 70 | | | | |01,02, | | | Standby current, TTL |ISB|OE = CE = VIH| 1, 2, 3 | 03 | | 1 | mA inputs 2/ |TTL |f = 0 MHz | |04,05, | | 2 | | |00-07= disabled | | 06 | | | | | | | 07 | | 15 | | | | |01,02, | | | Standby current, CMOS |ISB|OE = CE = VIH| 1, 2, 3 | 03 | | 140 | A inputs 4/ |

29、CMOS |f = 0 MHz | |04,05, | | 200 | | |00-07= disabled | | 06 | | | | | | | 07 | | 500 | VPPread current 5/ |IPP|VPP= VCC| 1, 2, 3 | All | | 100 | A | | | | | | | | | | | | | Input low voltage |VIL|VPP= VCC| 1, 2, 3 | All |-0.5 | 0.8 | V +10% supply 6/ | | | | | | | | | | | | | | | | | | | | | Input

30、 high voltage |VIH|VPP= VCC| 1, 2, 3 | All | 2.0 | VCC| V +10% supply 6/ | | | | | | +0.5 | | | | | | | | | | | | | | | Output low voltage |VOL|VIL= 0.8 V, VIH= 2.0 V | 1, 2, 3 | 01-06 | | 0.45 | V | |IOL= 2.1 mA | | | | | | | | | 07 | | 0.4 | | | | | | | | Output high voltage |VOH|VIL= 0.8 V, VIH=

31、2.0 V | 1, 2, 3 | All | 2.4 | | V | |IOH= -400 A | | | | | | | | | | | | Output short-circuit |IOS| | 1, 2, 3 | All | | 100 | mA current | 6/ | | | | | | | | | | | | See footnotes at end of table.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDA

32、RD MICROCIRCUIT DRAWING SIZE A 85102 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. | | Conditions | | | | Test |Symbol | -55C TC +125C | Group A |Device | Limits | | | 4.5 V VCC 5.5 V |subgr

33、oups | type | |Unit | | unless otherwise specified | | | Min | Max | | | | | | | | VPPread voltage 7/ |VPP| | 1, 2, 3 | All |VCC| VCC| V | | | |-0.7 | | Input capacitance |CIN|VIN= 0 V, See 4.3.1c | 4 | All | | 10 | pF | | | | | | | Output capacitance |COUT|VOUT= 0 V, See 4.3.1c | 4 | All | | 12 | |

34、 | | | | | | | | | | | | Functional tests | |See 4.3.1e | 7, 8 | All | | | | | | | 04 | | 90 | ns Address to output |tACC|CE = OE = VIL|9, 10, 11 | 01 | | 250 | delay 8/ 9/ | | | | 02 | | 350 | | | | | 03 | | 200 | | | | | 05 | | 120 | | | | | 06 | | 150 | | | | | 07 | | 70 | | | | | 04 | | 90 | ns

35、CE to output delay |tCE|OE = VIL|9, 10, 11 | 01 | | 250 | 8/ 9/ | | | | 02 | | 350 | | | | | 03 | | 200 | | | | | 05 | | 120 | | | | | 06 | | 150 | | | | | 07 | | 70 | | | | |04, 07 | | 30 | ns OE to output delay |tOE|CE = VIL|9, 10, 11 | 01 | | 100 | 8/ 9/ | | | | 02 | | 120 | | | | | 03 | | 75 | |

36、 | | | 05 | | 35 | | | | | 06 | | 45 | | | | |04, 07 | 0 | 25 | ns OE high to output |tDF|CE = VIL|9, 10, 11 |01, 03 | 0 | 55 | float 8/ 9/ | 6/ | | | 02 | 0 | 105 | | | | | 05 | 0 | 35 | | | | | 06 | | 40 | | | | | | | | Output hold from |tOH|CE = OE = VIL|9, 10, 11 | 01-06 | 0 | | ns addresses, CE

37、 or OE | 6/ | | | | | | whichever occurred | | | | 07 | 10 | | first 8/ 9/ | | | | | | | | | | | | | | 1/ Pins not tested are all at GND and 5.5 V respectively. 2/ TTL inputs: Specify VILand VIHlevels. 3/ CMOS inputs: GND +0.2 V to VCC+0.2 V. 4/ CE = VCC+0.2 V. All other inputs can have any value wi

38、thin specified limits. 5/ Maximum active power usage is the sum of IPP+ ICC. 6/ If not tested, shall be guaranteed to the limits specified in table I. 7/ VPPmay be connected directly to VCCexcept during programming. 8/ Outputs shall be loaded in accordance with figure 3. 9/ See figure 4.Provided by

39、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85102 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 6 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herei

40、n, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are descri

41、bed in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. 3.5.1 Certification/compliance mark. The compliance mark for device class M shall be a “C“ as

42、 required in MIL-PRF-38535, Appendix A. For Class Q product built in accordance with A.3.2.2 of MIL-PRF-38535 or other alternative approved by the Qualifying Activity, the “QD“ certification mark shall be used in place of the “QML“ or “Q“ certification mark. 3.6 Certificate of compliance. A certific

43、ate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers pro

44、duct meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notifica

45、tion of change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent and the acquiring activity retain the option to review the manufacturers facility and applicable required documentat

46、ion. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Processing EPROMS. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.10.1 Erasure of EPROMS. When specified, devices shall be erased in accordance with the procedures and characteristics specified by the manufacturer. 3.10.2 Programmability of EPROMS. When speci