DLA SMD-5962-10243 REV A-2013 MICROCIRCUIT CMOS LINEAR ANALOG MULTIPLEXER 16 CHANNEL +3 3 TO +5 VOLT MONOLITHIC SILICON.pdf

《DLA SMD-5962-10243 REV A-2013 MICROCIRCUIT CMOS LINEAR ANALOG MULTIPLEXER 16 CHANNEL +3 3 TO +5 VOLT MONOLITHIC SILICON.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-10243 REV A-2013 MICROCIRCUIT CMOS LINEAR ANALOG MULTIPLEXER 16 CHANNEL +3 3 TO +5 VOLT MONOLITHIC SILICON.pdf（21页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Table I: Corrected the max limit for the test +ICC,changed from “300 A“ to “800 A“. Table I: Added additional test conditions for the Switch ON resistance test. Updated footnotes in section 1.5. Made clarifications to table IIIA and table IV. Upd

2、ated section 4.3.5. -sld 13-09-30 Charles F. Saffle REV SHEET REV A A A A A A SHEET 15 16 17 18 19 20 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Steve L. Duncan DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mi

3、l/ STANDARD MICROCIRCUIT DRAWING CHECKED BY Greg Cecil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A APPROVED BY Charles F. Saffle MICROCIRCUIT, CMOS, LINEAR, ANALOG MULTIPLEXER, 16 CHANNEL, +3.3 TO +5 VOLT, MONOLITHIC SILICON DRAWING APPROVA

4、L DATE 13-03-27 REVISION LEVEL A SIZE A CAGE CODE 67268 5962-10243 SHEET 1 OF 20 DSCC FORM 2233 APR 97 5962-E572-13Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10243 DLA LAND AND MARITIME COLUMBUS, OHIO 43

5、218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available and are reflected in the Part or Identifying Number (PIN)

6、. When available, a choice of radiation hardness assurance levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 H 10243 01 K X C Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) desig

7、nator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Radiation hardness assurance (RHA) designator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s).

8、 The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 RHD5920 Analog multiplexer, 16 channel 02 RHD5921 Analog voltage multiplexer, buffered, 16 channel 03 RHD5922 Analog multiplexer, sample-and-hold, 16 channel 1.2.3 Device class designator. Th

9、is device class designator shall be a single letter identifying the product assurance level. All levels are defined by the requirements of MIL-PRF-38534 and require QML Certification as well as qualification (Class H, K, and E) or QML Listing (Class G and D). The product assurance levels are as foll

10、ows: Device class Device performance documentation K Highest reliability class available. This level is intended for use in space applications. H Standard military quality class level. This level is intended for use in applications where non-space high reliability devices are required. G Reduced tes

11、ting version of the standard military quality class. This level uses the Class H screening and In-Process Inspections with a possible limited temperature range, manufacturer specified incoming flow, and the manufacturer guarantees (but may not test) periodic and conformance inspections (Group A, B,

12、C, and D). E Designates devices which are based upon one of the other classes (K, H, or G) with exception(s) taken to the requirements of that class. These exception(s) must be specified in the device acquisition document; therefore the acquisition document should be reviewed to ensure that the exce

13、ption(s) taken will not adversely affect system performance. D Manufacturer specified quality class. Quality level is defined by the manufacturers internal, QML certified flow. This product may have a limited temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted wit

14、hout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10243 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator

15、Terminals Package style X See figure 1 24 Flat package with formed leads 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 1.3 Absolute maximum ratings. 1/ Supply voltage (VCC) +7.0 V dc Digital input overvoltage range: VEN , VA (device types 01 and 02) . ( GND - .4)V VSH VA

16、 (device type 03) . ( GND - .4)V Analog input overvoltage range . ( GND - .4)V Power dissipation (PD): Device types 01, 02, and 03 . 200 mW Thermal resistance junction-to-case (JC) 5 C/W Storage temperature -65C to +150C Lead temperature (soldering, 10 seconds) +300C 1.4 Recommended operating condit

17、ions. Supply voltage range (VCC) . +3.0 V to +5.5 V dc Logic low level voltage : VEN,VA (device types 01 and 02) .3 VCCVSH,VA (device type 03) . .3 VCC Logic high level voltage: VEN,VA (device types 01 and 02) .7 VCCVSH,VA (device type 03) . .7 VCC Case operating temperature range (TC). -55C to +125

18、C 1.5 Radiation features. 2/ Maximum Total Ionizing Dose (TID) (dose rate = 50 - 300 rad(Si)/s): In accordance with MIL-STD-883, method 1019, condition A. 1 Mrad(Si) Enhanced Low Dose Rate Sensitivity (ELDRS) . 3/ Single Event Latchup (SEL) . 100 MeV-cm2/mg 4/ Neutron Displacement Damage ( 1 x 1014

19、neutrons/cm2) 3/ 1/ Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ See section 4.3.5 for the manufacturers radiation hardness assurance analysis and testing. 3/ Not test

20、ed, Immune by 100 percent CMOS technology. 4/ Single Event Latchup (SEL) immunity is accomplished by double, fully enclosing, guard rings in the CMOS design layout. The guard rings eliminate the parasitic pnpn structure that is responsible for latchup in CMOS circuits. This limit is guaranteed by de

21、sign or process, but not tested. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10243 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.

22、1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPE

23、CIFICATIONS MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microci

24、rcuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a confl

25、ict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item per

26、formance requirements for device classes D, E, G, H, and K shall be in accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 shall include the performance of all tests herein or as designated in the device manufacturers Quality Management (QM) plan or as designated for the applicable device c

27、lass. The manufacturer may eliminate, modify or optimize the tests and inspections herein, however the performance requirements as defined in MIL-PRF-38534 shall be met for the applicable device class. In addition, the modification in the QM plan shall not affect the form, fit, or function of the de

28、vice for the applicable device class. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Termin

29、al connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3. 3.2.4 Switching test waveform(s). The switching test waveform(s) shall be as specified on figure 4. 3.2.5 Block diagram. The block diagram(s) shall

30、be as specified on figure 5. 3.2.6 Radiation exposure circuits. The radiation exposure circuits shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics.

31、Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full specified operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electric

32、al tests for each subgroup are defined in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10243 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.5 Mark

33、ing of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers vendor similar PIN may also be marked. 3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the ma

34、nufacturer of the device described herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot sample, for each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for those which,

35、 if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made available to the preparing activity (DLA Land and Maritime -VA) upon request. 3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer

36、in order to supply to this drawing. The certificate of compliance (original copy) submitted to DLA Land and Maritime -VA shall affirm that the manufacturers product meets the performance requirements of MIL-PRF-38534 and herein. 3.8 Certificate of conformance. A certificate of conformance as require

37、d in MIL-PRF-38534 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10243 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LE

38、VEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C VCC= +5 V unless otherwise specified Group A subgroups Device types Limits Unit Min Max Supply currents 1/ +ICCEN= .3 VCC1,2,3 01 10 800 A 02 0.5 5 mA 03 10 100 A +ISBY EN= .7 VC

39、C1,2,3 01 10 200 A 02 10 500 Address input 1/ currents IALVA= .3 VCC1 All -5 5 nA 2 All -50 50 IAH VA= .7 VCC1 All -5 5 nA 2 All -50 50 Enable input 1/ current IENL VEN = .3 VCC1 01,02 -5 5 nA 2 -50 50 IENHVEN = .7 VCC1 01,02 -5 5 nA 2 -50 50 Sample -and-Hold input current ISH VSH = .3 VCC 1 03 -5 5

40、 nA 2 -50 50 VSH = .7 VCC 1 -5 5 2 -50 50 Input leakage current (CH0 - CH15) 1/ IINLK5 VIN= +5 V, VEN= .7 VCC, output and all unused MUX inputs under test = 0 V 1 01,02 -5 5 nA 2 -50 50 VIN= +5 V,VSH = .7 VCC 1 03 -5 5 2 -50 50 IINLK0 VIN= 0 V, VEN= .7 VCC, output and all unused MUX inputs under tes

41、t = +5 V 1 01 -5 5 nA 2 -50 50 Output leakage current 1/ IOUTLK VOUT= +5 V, VEN= .7 VCC, All inputs grounded except channel being tested 1 01 -5 5 nA 2 -50 50 Tri-state, VEN .7 VCC1 02 -5 5 2 -50 50 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted w

42、ithout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10243 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C VCC= +5 V unless otherwise spec

43、ified Group A subgroups Device types Limits Unit Min Max Output on voltage VON1VIN= +5 V, RL= 10 k 1,2,3 02,03 4.8 5.1 V VON2VIN= +5 V, RL= 1 k 4.35 4.65 VON3VIN= +3.3 V, RL= 10 k 3.2 3.4 Input load capacitance CIN 1,2,3 03 35 pF Switch ON 1/ resistance RDSONVIN= 0 V, VEN = .3 VCC, IOUT= +1 mA 1 01

44、750 2 1000 3 500 VIN= +2.5 V, VEN = .3 VCC, IOUT= -0.6 mA 1 750 2 1000 3 500 VIN= +5 V, VEN = .3 VCC, IOUT= -1 mA 1 750 2 1000 3 500 Address to output delay tAHLRL= 10 k, CL= 50 pF, See figure 4 9,11 01 10 150 ns 10 10 200 9,10,11 02,03 1 3 s tALHRL= 10 k, CL= 50 pF, See figure 4 9,11 01 10 150 ns 1

45、0 10 200 9,10,11 02,03 1 3 s tONENRL= 1 k, CL= 50 pF, See figure 4 9,11 01 10 150 ns 10 10 200 9,10,11 02 .8 2.5 s tOFFENRL= 1 k, CL= 50 pF, See figure 4 9,10,11 01 10 200 ns 02 100 350 Droop rate DR RL= 1 k, CL= 50 pF, See figure 4 9,10,11 03 0.1 V/s Data setup time tDS RL= 1 k, CL= 50 pF, See figu

46、re 4 9,10,11 03 150 ns Data hold time tDH RL= 1 k, CL= 50 pF, See figure 4 9,10,11 03 150 ns Output slew rate tS9,10,11 02 1.8 4 V/s 1/ These devices have been tested to (2 Mrad(Si) to Method 1019, condition A of MIL-STD-883 at +25C for these parameters to assure the requirements of RHA designator l

47、evel “H” (1Mrad(Si) are met. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10243 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 Case X Symbol Inches Millimete

48、rs Min Max Min Max A .105 2.68 A1 .030 REF .76 REF A2 .017 .027 .43 .69 A3 .012 .30 b .015 .019 .38 .48 c .0068 .0092 .173 .234 D .614 15.60 e .050 BSC 1.27 BSC e1 .550 BSC 13.97 BSC E .300 7.62 E1 .394 .419 10.01 10.64 E2 .346 REF 8.79 REF NOTES: 1. Location of the pin 1 marking. The ESD symbol may be used as the pin 1 marking. 2. The U.S. preferred system of measurement is the metric SI. This item was designed using inch-pound un