DLA MIL-M-38510 178A-1984 MICROCIRCUITS DIGITAL CMOS MULTIPLEXERS DEMULTIPLEXERS MONOLITHIC SILICON POSITIVE LOGIC《正逻辑单片硅多路复用器 多路信号分离器 CMOS数字微电路》.pdf
《DLA MIL-M-38510 178A-1984 MICROCIRCUITS DIGITAL CMOS MULTIPLEXERS DEMULTIPLEXERS MONOLITHIC SILICON POSITIVE LOGIC《正逻辑单片硅多路复用器 多路信号分离器 CMOS数字微电路》.pdf》由会员分享,可在线阅读,更多相关《DLA MIL-M-38510 178A-1984 MICROCIRCUITS DIGITAL CMOS MULTIPLEXERS DEMULTIPLEXERS MONOLITHIC SILICON POSITIVE LOGIC《正逻辑单片硅多路复用器 多路信号分离器 CMOS数字微电路》.pdf(90页珍藏版)》请在麦多课文档分享上搜索。
1、MI L-M-38510/178A 30 April 1984 StDING MIL-M-38510/178 28 June 1979 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, CMOS, MULTIPLEXERS/DEMULTIPLEXERS MONOLITHIC SILICON, POSITIVE LOGIC This specification is approved for use by all :Depart- ments and Agencies of the Department of defense. I 1. SCOPE 1
2、.1 Scope. This specification covers the detail requirements for monolithic, sili- con, CMOS logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. 1.2 Part number. The part number shall be in acco
3、rdance with MIL-M-38510. 1.2.1 Device type. The device type shall be as follows: Devi c e type Circuit o1 Single 15-channel MUX/DEMUX o2 Differential 8-channel MUX/DEMUX 03 Quad 2-1 ine-to-1-1 ine data selector/MUX 1.2.2 Device class. The device class shall be the product assurance level as defined
4、in MIL-M-38510. 1.2.3 Case outline. The case outline shall be designated as follows: Outline letter Case outline (see MIL-M-38510, appendix C) E D-2 (16-lead, 1/4“ x 7/8“), dual-in-line package F F-5 (16-lead, 1/4“ x 3/8“), flat package J D-3 (24-1 ead, 1/2“ x 1-1/4“) , dual-in-1 ine package K F-6 (
5、24-lead, 3/8“ x 5/8“), flat package Z F-8 (24-leadY 1/4“ x 3/8“), flat package X F-5 (16-lead, 1/4“ x 3/8“), flat package, except A Y F-6 (24-lead, 3/8“ x 5/8“), flat package, except A U F-8 (24-lead, 1/4“ x 3/8“), flat package, except A dimension = 0.1“ (2.54 mm) max dimension = 0.1“ (2.54 mm) max
6、dimension = 0.1“ (2.54 mm) max NOTES : 1. As an exception to nickel plate or undercoating paragraph of MIL-M-38510, for case outlines X, Y, and U only, the leads of bottom brazed ceramic packages (i.e., configuration 2 of case outlines F-5, F-6, and F-8) may have electroless nickel undercoating whic
7、h shall be 50 to 200 microinches (1.27 to 5.08 vm) thick provided the lead finish is hot solder dip (i.e., finish letter A) and proyided that, after any lead forming, an additional hot solder dip coating is applied which shall extend from the outer tip of the lead to no more than 0.015 inch (0.38 mm
8、) from the package edge. dimension may go to .O00 inch (.O0 mm) mimimum. 2. For bottom or side brazed packages, case outlines F, Y, and U only, the S1 Beneficial comments (recommendations, additions, deletions) and any perti- nent data which may be of use in improving this document should be address
9、ed to: George C, Marshall Space Flight Center, National Aeronautics and Space Administration, ATTN: EG02, Marshall Space Flight Center, AL 35812 by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter. r THIS DOCUMEN
10、T CONTAINS PAGES FSC 5962 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-M-38510/17BA 57 W 7777706 0060255 1.3 Absolute maximum ratings. Supply voltage range (VDD-Vss)- - - - - - Input current (each input)- - - - - - - - Input voltage range - -
11、- - - - - - - - - Storage temperature range - - - - - - - - Maximum power dissipation (PD) - - - - - Lead temperature (sol deri ng , 10 seconds) - Thermal resistance, junction-to-case- - - Junction temperature (TJ) - - - - - - - - 1.4 Recommended operating conditions. supply voltage range (v0-v)- -
12、- - - - - Low level input voltage range (VIL) - - - - -0.5 V to +18 V i10 mA 200 mW +3OO0C (See MIL-M-38510, appendix C) +175C 4.5 V to 15 V 0-1.5 V dc Q VDD = 5 V dc, VOL = 10% VDD, VOH = 90% v 0-4.0 V dc 8DY = 15 V dc, 0-2.0 V dc VD - 10 V dc 3.5-5.0 V dc Q IDO = 5 V dc, VOL = 10% VDD, v H = 90% V
13、D 1P.O-15.0 V 8.0-10.0 V dc Q VDD = 10 V dc -55C to +125OC VDD = 15 V dc, High level input voltage range (VIH)- - - - Ambient operating temperature range (TA)- - 2. APPLICABLE DOCUMENTS 2.1 Government specifications and standards Unless otherwise specified, the following specifications and standards
14、, of the issue listed in that issue of the Department of Defense Index of Specifications and Standards specified in the solicitation, form a part of this specification to the extent specified herein. SPEC I FICAT ION MILITARY MI L-M- 38510 - Microcircuits, General Specification for. STANDARD MI L IT
15、ARY MI L-STD-883 - Test Methods and Procedures for Microelectronics. (Copies of specifications, standards, handbooks, drawings, and publications required by manufacturers in connection with specific acquisition functions should be obtained from the contracting activity or as directed by the contract
16、ing officer.) 2.2 Order of precedence. In the event of a conflict between the text of this specification and the references cited herein, the text of this specification shall take precedence. 3. REOU IREMENTS 3.1 Detail specification. The individual item requirements shall be in accordance with MIL-
17、M-38510, and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-M-38510 and herein. Although eutectic die bonding is preferred, epoxy die bonding may be performed. However, the resin !sed shall be Dup
18、ont 5504 Conductive Silver Paste, or equivalent, which is cured at 200 C *1D C for a minimum of 2 hours. The use of equivalent epoxies or cure cycles shall be approved by the qualifying activity. Equivalency shall be demonstrated in data submitted to the qualifying activity for verification. Provide
19、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-3.2.1 Terminal connections. The terminal connections shall be as specified on * 3.2.2 Logic diagrams. The logic diagrams shall be as specified on figure 2. figure 1. 3.2.3 Truth tables. The truth tables shall
20、be as specified on figure 3. 3.2.4 Schematic circuits. The schematic circuits shall be submitted to the preparing activity prior to inclusion of a manufacturers device in this specifi: cation and shall be submitted to the qualifying activity as a prerequisite for qualification. All qualified manufac
21、turers schematics shall be maintained and avail ab1 e upon request. 3.2.5 Case outline. The case outline shall be as specified in 1.2.3. 3.3 Lead material and finish. The lead material and finish shall be in accordance with MIL-M-38510 and 6.4 herein. 3.4 Electrical performance characteristics. Unle
22、ss otherwise specified, the electrical performance characteristics are as specified in table I, and apply over the full recommended ambient operating temperature range. device class shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table III. 3.5 E
23、lectrical test requirements. The electrical test requirements for each 3.6 Marking. Marking shall be in accordance with MIL-M-38510. 3.6.1. Total dose radiation hardness identifier. Total dose radiation hardness identifier shall be in accordance with MIL-M-38510 and 4.5.4 herein. 3.6.2 Serialization
24、. All class S devices stiall be serialized in accordance with MI L-M- 38510. 3.6.3 Correctness of indexing and marking. All devices shall be subjected to the final electrical tests specified in table II after part number marking to verify .that they are correctly indexed and identified by part numbe
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