DLA DSCC-VID-V62 12630-2012 MICROCIRCUIT DUAL CHANNEL DIGITAL ISOLATOR MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Orig
2、inal date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DUAL CHANNEL DIGITAL ISOLATOR, MONOLITHIC SILICON 12-10-09 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12630 REV PAGE 1 OF 13 AMSC N/A 5962-V005-13 Provided by IHSNot for ResaleNo reproduction or netwo
3、rking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12630 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance dual channel digital isolator microcircuit, with an operating temperatu
4、re range of -55C to +105C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12630 - 01 X B Drawing Device typ
5、e Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 ADuM1200-EP Dual channel digital isolator 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 8
6、 JEDEC MS-012-AA Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot
7、for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12630 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage, (VDD1, VDD2) . -0.5 V to +7.0 V 2/ Input voltage, (VIA, VIB) -0.5 V to VDDI+ 0
8、.5 V 2/ 3/ Output voltage, (VOA, VOB) . -0.5 V to VDDO+0.5 V 2/ 3/ Average output current per pin (IO) -11 mA to +11 mA 4/ Common mode transients (CML, CMH) -100 kV/s to +100 kV/s 5/ Ambient operating temperature, (TA) . -55C to +125C Storage temperature, (TST) -55C to 150C 1.4 Recommended operating
9、 conditions. Supply voltage, (VDD1, VDD2) . 2.7 V to 5.5 V 2/ Input signal rise and fall times . 1.0 ms Operating temperature, (TA) -55C to +105C 1.5 Package characteristics. Resistance (Input to output), RI-O . 1012 6/ Capacitance (Input to output) CI-O . 1.0 pF (at f = 1 MHz) Input capacitance, CI
10、. 4.0 pF Junction to case thermal resistance,(Side 1) JCI46 C/W 7/ Junction to case thermal resistance,(Side 2) JCO. 41 C/W 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are availab
11、le online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operat
12、ion of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ All voltages are relative to their respective ground. 3/ VDDIand VDD
13、Orefer to the supply voltages on the input and output sides of a given channel, respectively. 4/ See FIGURE 6 for maximum rated current values for various temperatures. 5/ Refers to common mode transients exceeding the absolute maximum ratings can cause latch up or permanent damage. 6/ The device is
14、 considered a 2-terminal device; Pin1, Pin2, Pin3, and Pin4 are shorted together, and Pin5, Pin6, Pin7, and Pin8 are shorted together. 7/ Thermocouple located at center of package underside. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AN
15、D MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12630 REV PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESD
16、S identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as speci
17、fied in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal conn
18、ections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 Truth table. The truth table shall be as shown in figure 4. 3.5.5 Functional block diagram. The functional block diagram shall be as shown in figure 5. 3.5.6 Thermal derating cu
19、rve. The thermal derating curve shall be as shown in figure 6. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12630 REV PAGE 5 TABLE I. Electrical performance characteristi
20、cs. 1/ Test Symbol Test conditions 4.5 V VDD1 5.5 V 4.5 V VDD2 5.5 V 2/ Limits Unit Min Typ Max 5 V OPERATIONS DC specifications Input supply current per channel, quiescent IDDI(Q)0.50 0.60 mA Output supply current per channel, quiescent IDDO(Q)0.19 0.30 mA Total supply current, two channels 3/ DC t
21、o 2 Mbps VDD1supply current VDD2supply current 10 Mbps VDD1supply current VDD2supply current 25 Mbps VDD1supply current VDD2supply current IDD1(Q) IDD2(Q) IDD1(Q) IDD2(Q) IDD1(Q) IDD2(Q) 4/ 4/ 5/ 5/ 6/ 6/ 1.1 0.5 4.3 1.3 10 2.8 1.4 0.8 5.5 2.0 13 3.4 mA Input currents IIA, IIB-10 +0.01 +10 A Logic h
22、igh input threshold VIH0.7 x 7/ V Logic low input threshold VIL0.3 x 7/ Logic high output voltages VOAH, VOBHIOX= -20 A, VIX= VIXH7/ - 0.1 5.0 IOX= -20 A, VIX= VIXH7/ - 0.5 4.8 Logic low output voltages VOAL, VOBLIOX= 20 A, VIX= VIXL0.0 0.1 IOX= 400 A, VIX= VIXL0.04 0.1 IOX= 4 mA, VIX= VIXL0.2 0.4 S
23、witching specifications Minimum pulse width 8/ PW 20 40 ns Maximum data rate 9/ 25 50 Mbps Propagation delay 10/ tPHL, tPLH20 45 ns Pulse width distortion, |tPLH tPHL| 10/ PWD 3 Propagation delay skew 11/ tPSK15 Channel to channel matching 12/ tPSKCD/tPSKOD3 Output rise/fall time (10% to 90%) tR/tF2
24、.5 Common mode transient immunity Logic high output 13/ Logic low output 13/ |CMH| |CML| VIX= VDD1, VDD2, VCM= 1000 V, transient magnitude = 800 V VIX= 0 V, VCM= 1000 V, transient magnitude = 800 V 25 25 35 35 kV/s Refresh rate fr1.2 Mbps Dynamic supply current per channel 14/ Input IDDI(D)0.19 mA/M
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