JEDEC JESD79-3F-2012 DDR3 SDRAM Specification.pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD79-3FJULY 2012JEDECSTANDARDDDR3 SDRAM Standard (Revision of JESD79-3E, July 2010)NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subsequently reviewed and

2、approvedby the JEDEC legal counsel.JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchaser in selecting and obtaining

3、with minimumdelay the proper product for use by those other than JEDEC members, whether the standard is tobe used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoptionmay involve patents or articles, materials, or processe

4、s. By such action JEDEC does not assumeany liability to any patent owner, nor does it assume any obligation whatever to parties adoptingthe JEDEC standards or publications.The information included in JEDEC standards and publications represents a sound approach toproduct specification and application

5、, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard orpublication may be further processed and ultimately become an ANSI standard.No claims to be in conformance with this standard may be made unless all requirem

6、ents stated inthe standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard orpublication should be addressed to JEDEC at the address below, or call (703) 907-7559 orwww.jedec.orgPublished byJEDEC Solid State Technology Association 20123103 North 10th Stree

7、t, Suite 240 SouthArlington, VA 22201This document may be downloaded free of charge; however JEDEC retains the copyright on thismaterial. By downloading this file the individual agrees not to charge for or resell the resultingmaterial.PRICE: Please refer to the currentCatalog of JEDEC Engineering St

8、andards and Publications online athttp:/www.jedec.org/Catalog/catalog.cfmPrinted in the U.S.A. All rights reservedPLEASE!DONT VIOLATE THE LAW!This document is copyrighted by JEDEC and may not bereproduced without permission.Organizations may obtain permission to reproduce a limited number of copies

9、through entering into a license agreement. For information, contact:JEDEC Solid State Technology Association3103 North 10th Street, Suite 240 SouthArlington, Virginia 22201or call (703) 907-7559This page left blank.JEDEC Standard No. 79-3FContentsi1 Scope12 DDR3 SDRAM Package Pinout and Addressing 3

10、2.1 DDR3 SDRAM x4 Ballout using MO-20732.11.1 512Mb 152.11.2 1Gb152.11.3 2Gb .152.11.4 4Gb .152.11.5 8Gb .163 Functional Description.173.1 Simplified State Diagram.173.3.1 Power-up Initialization Sequence .193.3.2 Reset Initialization with Stable Power213.4.1 Programming the Mode Registers 223.4.2 M

11、ode Register MR0233.4.3 Mode Register MR1273.4.4 Mode Register MR2303.4.5 Mode Register MR3324 DDR3 SDRAM Command Description and Operation.334.1 Command Truth Table .334.3 No OPeration (NOP) Command 364.4 Deselect Command 364.6.1 DLL “on” to DLL “off” Procedure.384.6.2 DLL “off” to DLL “on” Procedu

12、re.394.8.1 DRAM setting for write leveling CWL = 5; ODTLon = AL + CWL - 2 = 6.0; ODTLoff = AL + CWL - 2 = 6 . . . . . . . . . . . 91Figure 77 Synchronous ODT example with BL = 4, WL = 7. . . . . . . . . . . . . . . . . . . . . . . . . 92Figure 78 ODT must be disabled externally during Reads by drivi

13、ng ODT low. (example: CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTLon = CWL + AL - 2 = 8; ODTLoff = CWL + AL - 2 = 8) . . . . . . . . . . . . 93Figure 79 Dynamic ODT: Behavior with ODT being asserted before and after the write . . . 96Figure 80 Dynamic ODT: Behavior without write command

14、, AL = 0, CWL = 5 . . . . . . . . . 96Figure 81 Dynamic ODT: Behavior with ODT pin being asserted together with write command for a duration of 6 clock cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Figure 82 Dynamic ODT: Behavior with ODT pin being asserted together with write

15、 command for a duration of 6 clock cycles, example for BC4 (via MRS or OTF), AL = 0, CWL = 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Figure 83 Dynamic ODT: Behavior with ODT pin being asserted together with write command for a duration of 4

16、clock cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Figure 84 Asynchronous ODT Timings on DDR3 SDRAM with fast ODT transition: AL is ignored . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100JEDEC Standard No. 79-3FList of

17、 FiguresviFigure 85 Synchronous to asynchronous transition during Precharge Power Down (with DLL frozen) entry (AL = 0; CWL = 5; tANPD = WL - 1 = 4) . . . . . . . . 102Figure 86 Synchronous to asynchronous transition after Refresh command (AL = 0; CWL = 5; tANPD = WL - 1 = 4) . . . . . . . . . . . .

18、 . . . . . . . . . . . . . . . . 103Figure 87 Asynchronous to synchronous transition during Precharge Power Down (with DLL frozen) exit (CL = 6; AL = CL - 1; CWL = 5; tANPD = WL - 1 = 9) . . . 104Figure 88 Transition period for short CKE cycles, entry and exit period overlapping (AL = 0, WL = 5, tAN

19、PD = WL - 1 = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Figure 89 ZQ Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Figure 90 Illustration of VRef(DC) tolerance and VRef ac-noise limits . . . . . . . . . . . . .

20、 . . . 115Figure 91 Definition of differential ac-swing and “time above ac-level” tDVAC . . . . . . . . 116Figure 92 Single-ended requirement for differential signals. . . . . . . . . . . . . . . . . . . . . . . . . 118Figure 93 Vix Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21、. . . . . . . . . . . . . . . . . . . . . . . . 119Figure 94 Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# . . . . . . . . 120Figure 95 Single-ended Output Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Figure 96 Differential Output Slew Rate

22、Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Figure 97 Reference Load for AC Timing and Output Slew Rate . . . . . . . . . . . . . . . . . . . . 124Figure 98 Address and Control Overshoot and Undershoot Definition . . . . . . . . . . . . . . . . 125Figure 99 Clock, Dat

23、a, Strobe and Mask Overshoot and Undershoot Definition . . . . . . . . . 126Figure 100 Output Driver: Definition of Voltages and Currents . . . . . . . . . . . . . . . . . . . . . . 127Figure 101 On-Die Termination: Definition of Voltages and Currents . . . . . . . . . . . . . . . . . 130Figure 102

24、ODT Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Figure 103 Definition of tAON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136Figure 104 Definition of tAONPD . . . . . . . . . . . . . . .

25、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136Figure 105 Definition of tAOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Figure 106 Definition of tAOFPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

26、. . . . . . . . . . . . 137Figure 107 Definition of tADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Figure 108 Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27、. . . . . . . . . . . . . . . . . . . . . 140Figure 109 Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140Figure 110 Illustration of nominal slew rate and tVAC for setup time tI

28、S (for ADD/CMD with respect to clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186Figure 111 Illustration of nominal slew rate for hold time tIH (for ADD/CMD with respect to clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29、. . . . . . . . . . . . . 187Figure 112 Illustration of tangent line for setup time tIS (for ADD/CMD with respect to clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188Figure 113 Illustration of tangent line for for hold time tIH (

30、for ADD/CMD with respect to clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189Figure 114 Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) . . . . . . . . . . . . . . . . . . . . . .

31、 . . . . . . . . . . . . . . . . . . . . . . . . . . 195Figure 115 Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196Figure 116 Illustration of tangent lin

32、e for setup time tDS (for DQ with respect to strobe) . . 197Figure 117 Illustration of tangent line for hold time tDH (for DQ with respect to strobe) . . 198JEDEC Standard No. 79-3FList of TablesviiTable 1 Input/output functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

33、. . . . . . . . . . 13Table 2 State Diagram Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Table 3 Burst Type and Burst Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Table 4 Additive Latency (AL) Sett

34、ings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Table 5 TDQS, TDQS# Function Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Table 6 Command Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35、 . . . . . . . . . . . . . . . . . 33Table 7 CKE Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Table 8 MR setting involved in the leveling procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Table 9 DRAM te

36、rmination function in the leveling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Table 10 Mode Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Table 11 Self-Refresh mode summary . . . . . . . . . . . . . . . . . . . . . .

37、. . . . . . . . . . . . . . . . . . . . . 47Table 12 MPR MR3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Table 13 MPR MR3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Table 14 Power

38、-Down Entry Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Table 15 Termination Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Table 16 Latencies and timing parameters relevant for Dynamic ODT

39、. . . . . . . . . . . . . . . . . . 94Table 17 Timing Diagrams for “Dynamic ODT”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Table 18 Asynchronous ODT Timing Parameters for all Speed Bins . . . . . . . . . . . . . . . . . . 100Table 19 ODT timing parameters for Power Down

40、(with DLL frozen) entry and exit transition period101Table 20 Absolute Maximum DC Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109Table 21 Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109T

41、able 22 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111Table 23 Single-Ended AC and DC Input Levels for Command and Address . . . . . . . . . . . 113Table 24 Single-Ended AC and DC Input Levels for DQ and DM . . . . . . . . . . . . . . . . . .

42、. . 114Table 25 Differential AC and DC Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Table 26 Allowed time before ringback (tDVAC) for CK - CK# and DQS - DQS#. . . . . . . 117Table 27 Single-ended levels for CK, DQS, DQSL, DQSU, CK#, DQS#, DQSL# or DQSU# . 118

43、Table 28 Cross point voltage for differential input signals (CK, DQS) . . . . . . . . . . . . . . . . . 119Table 29 Differential Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Table 30 Single-ended AC and DC Output Levels. . . . . . . . . . . . . . .

44、. . . . . . . . . . . . . . . . . . 121Table 31 Differential AC and DC Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Table 32 Single-ended Output Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Table 33 Output Slew Rate (Sing

45、le-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Table 34 Differential Output Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Table 35 Differential Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .

46、 . . . . . . . . . . . . . 123Table 36 AC Overshoot/Undershoot Specification for Address and Control Pins. . . . . . . . . 125Table 37 AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask . . . . . 126Table 38 Output Driver DC Electrical Characteristics, assuming RZQ= 240 W ; entir

47、e operating temperature range; after proper ZQ calibration128Table 39 Output Driver Sensitivity Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129Table 40 Output Driver Voltage and Temperature Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . 129Table 41

48、ODT DC Electrical Characteristics, assuming RZQ= 240 W +/- 1% entire operating JEDEC Standard No. 79-3FList of Tablesviiitemperature range; after proper ZQ calibration131Table 42 ODT Sensitivity Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Table

49、 43 ODT Voltage and Temperature Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Table 44 ODT Timing Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Table 45 Reference Settings for ODT Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . 135Table 46 Timings used for IDD and IDDQ Measurement-Loop Patterns for 800/1066/1333/16001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .