JEDEC JEP170-2013 Guidelines for Visual Inspection and Control of Flip Chip Type Components (FCxGA).pdf
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1、 JEDEC PUBLICATION Guidelines for Visual Inspection and Control of Flip Chip Type Components (FCxGA) JEP170 JANUARY 2013 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directo
2、rs level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assistin
3、g the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may invo
4、lve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a soun
5、d approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conforma
6、nce with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for
7、 alternative contact information. Published by JEDEC Solid State Technology Association 2013 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual a
8、grees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Associatio
9、n 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 170 -i- Guidelines for Visual Inspection and Control of Flip Chip Type Components (FCxGA) Introduction With the increased presence of fli
10、p chip type components - ball grid array (FCBGA), pin grid array (FCPGA), land grid array (FCLGA) - in electronic devices ranging from thin/light portable to massively parallel data centers, it is critical to offer clear guidelines for visual inspection and control that ensures quality and reliabili
11、ty of these components. JEDEC Publication No. 170 -ii- Guide(From JEDReliability1 SThis publimpact enconsidereproducts. or visual nin actual p2 Tball grid via a rectaflip chip dsolder joinflip chip pNOTE 1 arrays (PGNOTE 2 constructioNOTE 3 fiducial mthe imagelines for ViEC BoD BaTest Methocope icat
12、ion provd-user produd visual noncFinally, it wonconformitroduct drawierms and Dearray (BGA)ngular array ie: An unpats. (Ref. JESackage (FCThe flip chip pA) per customThe lowercasen, e.g., B for bFCBGA packaarker; fiducproduced forsual Inspecllot JCB-12-ds for Packagides descriptcts and/or apponformi
13、ties sill depict a mies and guidangs and specfinitions package: Aof ball-type cckaged die wD22-B109A)xGA): A pacackage may ber requirement“x” in the abball, L for landges typically hial: An objeuse as a pointion and Co50, formulateed Devices.)ion of defeclications. It ince they shoethod for visunce
14、for dispoifications. package in wonnections, ahose electric. kage consistie configured ts. reviation shou, P for pin. ave a filled epct, placed in t of referencntrol of Flid under the cts observed will also provuld be less dal inspectionsition. Offichich the extll on a commal interconneng of a faced
15、o ball grid arrald be replacedoxy that is disthe field of ve or a measurp Chip Typognizance ofin FCxGA cide illustratiisruptive of qthat can be uial criteria foernal connecon plane. ctions to a suown flip chipys (BGA), lanby a capital lepensed betweiew of an imae. JEDEC Ppe Componethe JC-14.1 ompone
16、nts ton on other duality or relitilized to ider product acctions to the pbstrate are fodie on an ord grid arrays (tter representien the die and aging systemublication NoPnts (FCxGSubcommittehat can adveefects that mability to cusntify these deptance shouackage are mrmed throughganic substraLGA), or
17、pin gng the applicathe substrate., that appears. 170 age 1 A) e on rsely ay be tomer efects ld be ade te. rid ble in JEDEC Publication No. 170 Page 2 2 Terms and dDefinitions (contd) field of view (in metrology): The area of the test sample under metrological examination. land grid array (LGA) packa
18、ge: A package in which the external connections to the package are made via a rectangular array of land-type connections, all on a common plane. organic substrate: A substrate with laminate materials constructed with glass fibers that are carbon-based epoxies. pin grid array (PGA) package: A package
19、 in which the external connections to the package are made via a rectangular array of pin-type connections, all on a common plane. 3 Informative Reference Documents JESD16-A, Assessment of Average Outgoing Quality Levels in Parts Per Million (PPM) JESD47, Stress-Test-Driven Qualification of Integrat
20、ed Circuits JESD22-B109A, Flip Chip Tensile Pull JESD22-B101B, External Visual Examination JESD22-B118, Semiconductor Wafer and Die Backside External Visual Inspection 4 Assembly Process Flow (illustration purpose) A typical assembly flow for flip chip packaging for FCxGA (FCBGA, FCLGA, and FCPGA) i
21、s shown in Figure 4.1. NOTE Steps in grey may/may not be part of the flow depending on package type. Yellow demarks focus of this document Figure 4.1 Assembly Process Flow 4.1 Wafer Dicing To mechanically separate the functional Die (Wafer = Individual Dice) Wafer Dicing Chip Attach Epoxy Underfill
22、Heat Spreader Attach Electrical Test Visual Inspection xGA Ball /Pin Attach JEDEC Publication No. 170 Page 3 4 Assembly Process Flow (illustration purpose) (contd) 4.2 Chip/Component Attach To place die on package and form the electrical and mechanical connections between the die/package by reflowin
23、g the solder at high temperature to form a high-quality solder joint. Die Side Capacitors can also be placed and joints formed at this operation. 4.3 Epoxy Underfill To fill the cavity under the die and around the die perimeter with epoxy. This seals the area and provides mechanical support for the
24、die-to- package interconnects. 4.4 Heat Spreader Attach/Cure Thermal interface material is placed on top of the die and the Heat Spreader is attached with sealant (and cured). This is done to control thermal performance especially for products which have higher rates of heat generation or are very t
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