JEDEC JEP122G-2011 Failure Mechanisms and Models for Semiconductor Devices.pdf
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1、JEDEC PUBLICATION Failure Mechanisms and Models for Semiconductor Devices JEP122G (Revision of JEP122F, November 2010) OCTOBER 2011 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board
2、 of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, a
3、nd assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adopti
4、on may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications repres
5、ents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be
6、in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Publishe
7、d by JEDEC Solid State Technology Association 2011 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resu
8、lting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without
9、 permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or call (703) 907-7559 JEDEC Publicat
10、ion No. 122G FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES Contents Page Foreword iii Introduction iii 1 Scope 1 2 Terms and definitions 1 3 Inclusions, deliberate omissions, and resources 5 4 The basic thermal acceleration equation 9 5 Models for common failure mechanisms 9 FEoL Failure M
11、echanisms 5.1 Time-Dependent Dielectric Breakdown (TDDB) gate oxide 9 5.2 Hot Carrier Injection (HCI) 14 5.3 Negative Bias Temperature Instability (NBTI) 17 5.4 Surface inversion (mobile ions) 20 5.5 Floating-Gate Nonvolatile Memory Data Retention 22 5.6 Localized Charge Trapping Nonvolatile Memory
12、Data Retention 26 5.7 Phase Change (PCM) Nonvolatile Memory Data Retention 27 BEoL Failure Mechanisms 5.8 Time-Dependent Dielectric Breakdown (TDDB) ILD/Low-k/Mobile Cu ion 30 5.9 Aluminum Electromigration (Al EM) 38 5.10 Copper Electromigration (Cu EM) 41 5.11 Aluminum and Copper Corrosion 43 5.12
13、Aluminum Stress Migration (Al SM) 48 5.13 Copper Stress Migration (Cu SM) 50 Packaging/Interfacial Failure Mechanisms 5.14 Fatigue failure due to temperature cycling and thermal shock 53 5.15 Interfacial failure due to temperature cycling and thermal shock 57 5.16 Intermetallic and oxidation failure
14、 due to high temperature 60 5.17 Tin Whiskers 62 5.18 Ionic Mobility Kinetics (PCB) Component Cleanliness 66 Statistics and Modeling Parameter Determination 5.19 Reliability data/analysis 69 5.20 Design of Experiments (DOE) for determination of modeling parameters 74 6 Activation energies and modeli
15、ng factors 76 Annexes Annex A List of references 81 Annex B Differences between JEP122G and JEP122F 96 -i- JEDEC Publication No. 122G -ii- FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES Contents Page Figures 5.1.1 Photograph of TDDB breakdown in a gate oxide mid-gate 13 5.5.1 Extrapolation
16、of SILC bit error rate 25 5.8.1 Time-Dependent Dielectric Breakdown (TDDB) in various dielectrics 30 5.8.2 Metal stack cross section/schematic 32 5.8.3 Normal distribution of breakdown voltage 33 5.8.4 Copper short/extrusion 34 5.9.1 Examples of Aluminum Electromigration 40 5.10.1 Examples of Copper
17、 Electromigration 43 5.11.1 Aluminum bond pad corrosion 47 5.11.2 Electrochemical reaction 47 5.11.3 Corrosion rate versus surface mobility 47 5.12.1 Examples of Aluminum Stress Migration 50 5.13.1 Examples of Copper Stress Migration 53 5.14.1 Examples of temperature cycling/thermal shock damage 57
18、5.15.1 Example of interfacial delamination after temperature cycling 60 5.17.1 SEM of Tin Whiskers on Matte Tin plated Alloy 42 leads 5.16.4 64 5.17.2 Optical Image of a Tin Whisker growing from Relay lead to case 5.16.3 64 5.17.3 FIB - matte tin whisker structure from a temperature cycled specimen
19、5.16.5 65 5.17.4 Optical Image - Tin Whisker growing from SAC 305 solder over Alloy 42 - matte tin 65 5.17.5 Optical image of Tin Whisker on a copper coupon with matte tin plating 5.16.4 65 5.17.6 8 mm long Tin Whisker growing from a bracket holding electronics in a frame. 65 5.17.7 Tin Whisker brea
20、king through 10 m Uralane 5750 coating (9 yr office storage) 5.16.3 65 5.18.1 Resistor corroded open due to trapped MSA residues in epoxy surface 3 67 5.18.2 Electrochemical migration between leads on a QFP 67 5.18.3 Leakage and corrosion problems with residues on tinned leads due to aggressive flux
21、 68 5.18.4 Leakage square brackets enclose citation numbers. All equation, citation, and figure numbers include the subclause number so that individual clauses can be modified without disturbing other clauses, except for page numbers. Thus, (5.3.2) is the 2nd equation in 5.3 and 5.11.5 is the 5th ci
22、tation in 5.11. The citations can be found in Annex A. -iii- JEDEC Publication No. 122G -iv- JEDEC Publication No. 122G Page 1 FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES (From JEDEC Board Ballot JCB-01-97, JCB-03-39, JCB-08-61, JCB-09-19, JCB-10-64, and JCB-11-74 formulated under the co
23、gnizance of JC-14.1 Subcommittee on Reliability Test Methods for Packaged Devices.) 1 Scope This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data
24、is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method. The models apply primarily to the following: a) Aluminum (doped with small amounts of Cu and/or Si) and copper alloy metallization b) Refractory metal barrier metals with
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