JEDEC JEP110-1988 Guidelines for the Measurement of Thermal Resistance of GaAs FETs《GaAs FETs的热阻测量导则》.pdf

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1、JEDEC PUBLICATION Guidelines for the Measurement of Thermal Resistance of GaAs FETs JEDEC Publication No. 110 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesNOTICE JEDEC Standards and Publications contain mate

2、rial that has been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. B JEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturer

3、s and purchasers, facilitating inter- changeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from m

4、anufacturing or selling products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members whether the standard is to be used either domestically or internationally. JEDEC Standards or Publications are adopted without reg

5、ard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC Standards or Publications. The information included in JEDEC

6、 Standards and Publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC Standard or Publication may be further processed and ultimately become

7、an EIA Standard. 1 Inquiries, comments, and suggestions relative to the content of this JEDEC Standard or Publication should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2001 Eye Street, N.W., Washington, D.C. 20006. COPYRIGHT 1988 ELECTRONIC INDUSTRIES ASSOCIATION Published by

8、 ELECTRONIC INDUSTRIES ASSOCIATION Engineering Department 2001 Eye Street, N.W. Washington, D.C. 20006 Printed in U.S.A. i, COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JEPLLO 88 = 3234600 0003229 3 JED$C,Publication No. 110 Page 1 GUIDELINES FOR MEASURNT OF.

9、T .THERMAb RESISTANCE.0F GaAs PETS 1. (From JEDEC ,Counc i 1 cognizance .of .JC-50: -. . iittee 0-n Gallium Arsnide, Compound Semiconductors.) FET failure mechanisms and failure rates have, in general,-,an exponential dependence on temperature (which is whytmperature-accelerated testing is successfu

10、l). Because of the exponential relationsh.ipbf failure rate with temperature, the,therma resistance should be referenced to the-hottest-part.of th,FET. Contributions ;to the thermal resistancein a l?ETarije from several sogrces including (see Figure 1 for definjtions; these guidelines primarily addr

11、ess channel-to-mounting s.urface thermai,resistance,._ROC for GaAs -. langed papkages) : .1 second and demand careful attention to mounting of the FET in order to avoid errors in measured thermal resistance due to improper flange-to-test fixture mounting. This thermal resistance is the one used to e

12、stimate channel temperatures. 1.3 Measurement Techniques Several measurement techniques for thermal resistance are in common use today. They are: (1) Electrical, or forward VGS, technique (2) IR (Infrared) technique (3) Liquid crystal techniques Only the first two are suitable for 100% screening and

13、 only the electrical technique is suitable for hermetically sealed packages. All techniques have the following steps in common: COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JEPLLO 88 m 3234b00 000323L L m JEDEC Publication No. 110 Page 3 1.3 Measurement Techni

14、ques (continued) (1) A known power is input for a known period of time (or until a steady-state condition is reached) (2) A change in channel temperature is measured (3) The thermal resistance calculation is made. Differences in results among the techniques arise because of differences in: (1) Heati

15、ng time (2) Temperature measurement accuracy (3) Temperature distribution across the FET. The ideal thermal resistance technique would accurately measure the temperature of the hottest spot in the FET in RF operation with the FET flange being held at a constant temperature. The measurement should no

16、t affect the devices operation nor alter it in any way and should be useable on 100% of the FETs. It should be useable on hermetically sealed FETs and provide a steady-state thermal resistance. None of the present techniques meet all of these criteria. Briefly their characteristics are: 1.3.1 Electr

17、ical Technique In this technique the change in forward-biased gate voltage (at a constant gate current) with a change in temperature is first measured. Then the change in forward-biased gate voltage AVGS, in response to a heating pulse is measured. The thermal resistance can then be calculated. The

18、heating pulse is obtained by applying a drain potential, VDS, during the heating period. The gate may be biased either positive or negative during the heating pulse. COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesJEDEC Publication No. 110 Page 4 1.3.1 Electrical Tec

19、hnique (continued) If it is positive IDSS. If- the FET temperature distr characteristics a accurate results. parallel and the then the drain current will be greater than has a simple gate with a uniform bution and uniform electrical ong its length this technique should give hannel temperatures and e

20、lectrical However, power FETs have many gates in characteristics are typically nonuniform. Consequently, this technique provides an “average“ channel temperature which is an average over the individual gate responses. A feature of the technique is that it can be applied to FETs in hermetic packages.

21、 This technique does not directly give hot-spot thermal resistance. 1.3.2 IR Technique In this technique the circuit heat sink is held at a known temperature, a known bias is applied to the FET and the resulting temperature at any point in the FET can be determined by measuring the IR radiation from

22、 the site. Consequently, this technique can be used to determine the thermal resistance related to the hottest spot on the FET. However, the hot-spot dimension is on the order of the channel dimension (length around one micrometer for X-band FETs) while the resolution for the IR microscopes is only

23、15 to 30 micrometers and is not expected to improve. Therefore, the IR temperature measured is an average temperature over a 15 to 30 micrometers spatial area that includes the channel. Within these limits this technique can also be used to determine the temperature differential across the FET. Disa

24、dvantages to this technique are that the FET chip must be exposed for the measurement and regions of varying emissivity (common to upright mounted FETs) can cause additional measurement errors if not handled properly. 1.3.3 Liquid Crystal Technique In this technique a liquid crystal is chosen which

25、has a transition in the desired temperature range. The FET is then coated with the material and, with the circuit heat sink temperature held constant, bias power is increased until a change in polarization (seen as a dark spot) is observed on some area of the FET. COPYRIGHT Electronic Industries All

26、ianceLicensed by Information Handling ServicesEIA JEPLLO 88 m 3234600 0003233 5 m JEDEC Pu,b1 icat ion No:. 110 Page 5 1.3.3 Liquid Crystal Technique (continued) Since the temperature at which this change occurs is accurat-ely known a thermal resistance can be calculated. -By observing the FET under

27、 a mircoscope (using visible,light) one-micrometer size features can be resolved. This technique can be used to determine hot spots and can be very-accurate. It is not normally used on deliverable FETs since the FET is contaminated with the liquid crystal. Also, the FET must be visible to make the m

28、easurement so hermetic parts cannot be examined. Other disadvantages are: (1) (2) . The liquid crystal can affect the temperature r. (3) Contamination can change the transition tempecaiure of All t*hree techniques are subject to measurement and interpretational difficulties and therefore careful -.

29、calibration and analysis are musts. Table 1 provides a summary of the three techniques. .*. , Only a limited temperature range of liquid cry.stals is available. distribution if improperly applied. . some liquid crystals. A thecmal resistance screen is a necessary, but not sufficient, screen for good

30、 die bonds (or source bpnds for . flip-chip FETs). A screen based on limiting the -temperature difference between the hottest and coldest .channels on the FET is also important to ensure a good bond. Wi th this background the following gui.de1 ines, goals and suggestions are proposed for thermal res

31、istance measurement. . -. COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JEPLLO 88 3234600 0003234 7 JEDEC Publication No. 110 Page 6 2. GUIDELINES (1) The thermal resistance measurement technique should be (2) Steady-state, as opposed to transient, ROCM should

32、be measured and provided for FETs intended for use in cw operation. (3) The temperature of the mounting surface (heat sink) to which the transistor flange is attached should be held constant during the RGCM measurement. (4) The RM should be measured at a channel temperature appropriate to the manufa

33、cturers suggested application temperature. The manufacturer should also provide data indicating the expected temperature variation of the thermal resistance over the operating temperature range of FET. applicable to deliverable parts. (5) If a technique is used that measures RM prior to the completi

34、on of processing, the manufacturer should verify that the subsequent processing does not affect %CM* information (for their chosen ROCMC technique) allowing correlation with other techniques. (7) The attachment technique, including screw size (if any) and torque or clamping pressure used to attach t

35、he transistor flange to the circuit heat sink during the R CM measurement, should be specified. (6) The manufacturer should provideor possess calibration (8) The conditions (flange and channel temperatures and bias levels) used to measure ROCM should be recorded and provided for each FET measured. c

36、oldest channel should be measured at the channel temperature used in the Roch measurement. (9) The temperature difference between the hottest and COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JEPLLO 88 m 3234b00 0003235 7 m . . -. JEDEC Publication No. 110 Page

37、 7 3. RECOMHENDATIONS - (1) Use IR technique to determine AT across the FET (bekore capping). .I (2) Use electrical or IR technique to measure RM. (3) Use .the liquid crystal technique to calibrate the IR (4) Use pulsed electrical technique for die attach (5) and electrical techniques. screening. Th

38、e RM should be meas-ured on -100% of deliverable; parts intended for applications requiring high reliability. n. .“ m: . . . . , , . . . , SUBSTRATE . . . . . . . . . . . . . FIGURE 1 Typical Construction of Upright FET Mounted On a Test Or Application Circuit (D = drain, G = gate, S = source) COPYR

39、IGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JEPLLO 88 3234600 000323b O Publication No. 110 Page 8 4. DESIRED GOALS FOR FUTURE GUIDELINES (1) The RWn4 obtained from the hottest spot on each FET should be measured and recorded. (2) Since the various measurement tec

40、hniques for thermal resistance use approximations to the true hot-spot temperature, the manufacturer should relate the results of his RM measurement to the true hot-spot temper ature. (3) The variation of RM with the RF operating parameters should be determined. COPYRIGHT Electronic Industries Allia

41、nceLicensed by Information Handling ServicesEIA JEPLLO m 323Yb00 0003237 2 m JEDEC Publication No. 110 Page 9 TABLE 1 Summary of RM Measurement Techniques Transient Production Use Technique Hottest spot RF Oper Correc DC Sealed FETs- Stead) State Yes Electrical I No No Cate positive Electrical 9 Gat

42、e negative No Yes Y es Y es No Y es Yes Yes Yes Y es No Y es (Aver age over 15 miaameter diameter, or larger, area) Yes Yes No No Yes IR Yes Y es No Liquid Crystal No Yes (Average over -1 micrometer diameter area) No Cm be No COPYRIGHT Electronic Industries AllianceLicensed by Information Handling Services