EN 165000-2-1996 en Film and Hybrid Integrated Circuits Part 2 Internal Visual Inspection and Special Tests《膜集成电路和混合集成电路 第2部分 内部目视检查和特殊试验》.pdf

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1、BRITISH STANDARD BS EN 165000-2:1996 Harmonized system of quality assessment for electronic components Film and hybrid integrated circuits Part 2: Internal visual inspection and special tests The European Standard EN 165000-2:1996 has the status of a British Standard ICS 31.200BS EN 165000-2:1996 Th

2、is British Standard, having been prepared under the direction of the ElectrotechnicalSector Board,waspublished under theauthority of the StandardsBoard and comes intoeffect on 15 October 1996 BSI 10-1998 The following BSI references relate to the work on this standard: Committee reference EPL/47/1 D

3、raft for comment 92/216399 DC ISBN 0 580 26182 4 Committees responsible for this British Standard The preparation of this British Standard was entrusted by Technical Committee EPL/47, Semiconductors, to Subcommittee EPL/47/1, Film and hybrid integrated circuits, upon which the following bodies were

4、represented: Federation of the Electronics Industry Ministry of Defence National Supervising Inspectorate (BSI Product Certification) Amendments issued since publication Amd. No. Date CommentsBSEN165000-2:1996 BSI 10-1998 i Contents Page Committees responsible Inside front cover National foreword ii

5、 Foreword 2 Text of EN 165000-2 5 List of references Inside back coverBS EN165000-2:1996 ii BSI 10-1998 National foreword This British Standard has been prepared by Subcommittee EPL/47/1 and is the English language version of EN 165000-2:1996, Film and hybrid integrated circuits Part 2: Internal vis

6、ual inspection and special tests published by the European Committee for Electrotechnical Standardization (CENELEC). A British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a

7、British Standard does not of itself confer immunity from legal obligations. Cross-references Publication referred to Corresponding British Standard BS EN 165000 Film and hybrid integrated circuits EN 165000-1:1996 BS EN 165000-1:1996 Generic specification. Capability approval procedure EN 165000-3:1

8、996 BS EN 165000-3:1996 Self-audit checklist and report for film and hybrid integrated circuit manufacturers EN 165000-4:1996 BS EN 165000-4:1996 Customer information, product assessment level schedules and blank detail specification Summary of pages This document comprises a front cover, an inside

9、front cover, pages i to ii, theENtitle page, pages2to 26, an inside back cover and a back cover. This standard has been updated (see copyright date) and may have had amendments incorporated. This will be indicated in the amendment table on theinside front cover.EUROPEAN STANDARD NORME EUROPENNE EURO

10、PISCHE NORM EN 165000-2 April 1996 ICS 31.200 Descriptors: Quality, generic specification, hybrid circuits English version Film and hybrid integrated circuits Part2:Internalvisualinspection and special tests This European Standard was approved by CENELEC on 1996-03-05. CENELEC members are bound to c

11、omply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Central

12、Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status

13、 as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland and United Kingdom. CENELEC European Committee for El

14、ectrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B-1050 Brussels 1996 Copyright reserved to CENELEC members Ref. No. EN 165000-2:1996 EEN 165000-2:1996 BSI 10-1998 2 Foreword This

15、European Standard was prepared by CLC/TC CECC SC 47AX (former CECC/WG 21), Film and hybrid integrated circuits. The text of the draft was submitted to the Unique Acceptance Procedure and was approved by CENELEC as EN 165000-2 on 1996-03-05. The following dates were fixed: The present standard, EN 16

16、5000-2 Film and hybrid integrated circuits Part 2: Internal visual inspection and special tests is intended to be read in conjunction with the other parts of EN 165000, which are: Part 1: Generic specification Capability approval procedure; Part 3: Self-audit checklist and report for film and hybrid

17、 integrated circuit manufacturers; Part 4: Customer information, product assessment level schedules and blank detail specification. Part 3 is primarily intended as a pro-forma for the manufacturer and is not considered essential for a customer in this form. Part 4 is considered an essential document

18、 for all users; in particular it includes a helpful introductory section which is aimed at potential customers and seeks to explain the underlying philosophy upon which the whole standard is based. Contents Page Foreword 2 Section 1. Internal visual inspection 1 General 5 1.1 Purpose 5 1.2 Sequence

19、of inspection 5 1.3 Inspection apparatus 5 1.4 Inspection environment 5 1.5 Magnification 5 1.6 Definitions 5 1.7 Interpretation 6 1.8 Alternative test methods 6 2 Substrate and processes 6 2.1 Substrate 6 2.2 Processes 6 2.2.1 Conductors 6 2.2.2 Isolating layer 7 2.2.3 Resistors 7 2.2.4 Foreign mat

20、erial 8 3 Assembly mechanical attachment and electrical connection of parts to the substrate 8 3.1 Added components 8 3.2 Assembly method 8 3.2.1 General 8 3.2.2 Soldering and eutectic attachment 8 3.2.3 Organic adhesive 8 4 Assembly mechanical attachment and electrical connection of substrate to pa

21、ckage 9 4.1 General 9 4.2 Soldering and organic adhesive 9 5 Wire interconnections 9 5.1 General 9 5.2 Gold ball and wedge bonds 9 5.3 Gold ball bonds 9 5.4 Tailless (crescent) bonds 10 5.5 Wedge bonds 10 5.6 Compound bonds 10 5.7 Beam lead bonds 10 5.8 Bonding wires 10 6 Foreign material 11 7 Selec

22、tive organic protection 11 Section 2. Radiographic inspection 1 General 24 latest date by which the ENhas to be implemented at national level by publication of an identical national standard or by endorsement (dop) 1997-03-01 latest date by which the national standards conflicting with the EN have t

23、o be withdrawn (dow) 1997-03-01EN165000-2:1996 BSI 10-1998 3 Page 2 Requirements 24 2.1 Views 24 2.2 Reports and records 24 2.3 Examination and acceptance criteria 24 Section 3. Particle impact noise detection (PIND) test 1 Object 25 2 General 25 3 Equipment 25 4 Test procedure 25 5 Failure criteria

24、 26 6 Lot acceptance 26 7 The detail specification 26 Figure 1 11 Figure 2 12 Figure 3 12 Figure 4 12 Figure 5 12 Figure 6 12 Figure 7 12 Figure 8 12 Figure 9 13 Figure 10 13 Figure 11 13 Figure 12 13 Figure 13 13 Figure 14 13 Figure 15 13 Figure 16 14 Figure 17 14 Figure 18 14 Figure 19 14 Figure 2

25、0 14 Figure 21 14 Figure 22 14 Figure 23 14 Figure 24 15 Figure 25 15 Figure 26 15 Figure 27 15 Figure 28 15 Figure 29 15 Figure 30 16 Figure 31 16 Page Figure 32 16 Figure 33 16 Figure 34 17 Figure 35 17 Figure 36 17 Figure 37 17 Figure 38 17 Figure 39 17 Figure 40 17 Figure 41 18 Figure 42 18 Figu

26、re 43 18 Figure 44 19 Figure 45 19 Figure 46 19 Figure 47 19 Figure 48 19 Figure 49 20 Figure 50 20 Figure 51 20 Figure 52 20 Figure 53 20 Figure 54 20 Figure 55 21 Figure 56 21 Figure 57 21 Figure 58 22 Figure 59 23 Figure 60 23 Table 1 Shaker frequencies 264 blankEN165000-2:1996 BSI 10-1998 5 Sect

27、ion 1. Internal Visual inspection 1 General 1.1 Purpose The purpose of these examinations is to check the internal materials, added components, construction and workmanship of film and hybrid integrated circuits. These examinations will normally be used prior to capping or encapsulation to detect an

28、d eliminate the circuits with internal defects that could lead to device failure in normal application. Other acceptance criteria may be agreed upon with the purchaser or supplier respectively. 1.2 Sequence of inspection The sequence which is presented is not a required order of examination and may

29、be varied at the discretion of the manufacturer. Any aspect which may be obscured by a subsequent assembly process shall be examined before that process. 1.3 Inspection apparatus The apparatus for this test shall include optical equipment capable of the specified magnification(s) and any visual stan

30、dards (gauges, drawings, photographs, etc.) necessary to perform an effective examination and enable the operator to make objective decisions as to the acceptability of the device being examined. Adequate fixtures shall be provided for handling devices during examination to promote efficient operati

31、on without inflicting damage to the units. 1.4 Inspection environment Under consideration. 1.5 Magnification “High magnification” (100 to 200 x) inspection is normally performed with a microscope perpendicular to the relevant surface with the device under illumination normal to the relevant surface.

32、 “Low magnification” (10 to 100 x) inspection is normally performed with a monocular, a binocular or a stereomicroscope at an appropriate angle and illumination. 1.6 Definitions 1.6.1 active circuit area all areas of functional circuit elements, operating metallization or any connected combinations

33、thereof 1.6.2 multi-layer metallization (for conductors) two or more layers of metal or any other material used for interconnections that are not isolated from each other 1.6.3 edge metallization metallization that electrically connects different layers of metallization on or within a substrate at i

34、ts edge 1.6.4 foreign material any material not used in the manufacture of the microcircuit or any in-built material that is displaced from its original or intended position within the microcircuit package. Foreign material that appears opaque under those conditions of lighting and magnification use

35、d in routine visual inspection shall be considered as conductive 1.6.5 protective layer (passivation) the layer of insulating material that protects part or all of the substrate area, including metallization, but excluding connecting pads, for example glassivation, solder resist, etc. 1.6.6 isolatin

36、g layer a layer used to isolate separate conductive or resistive levels 1.6.7 kerf the slit or cut made by a material-removing process (for example laser or abrasive trimming) 1.6.8 multi-level metallization (for conductors) two or more levels of metal or any other material used for interconnections

37、 that are isolated from each other by a grown or deposited insulating material and interconnected for example by vias or edge metallization 1.6.9 bond pad area that area of exposed metallization which is not covered by passivation 1.6.10 compound bond bonding of one bond on top of another bond 1.6.1

38、1 through hole metallization metallization that electrically connects different levels of metallization on or within a substrate via a hole or holesEN 165000-2:1996 6 BSI 10-1998 1.6.12 scratch any tearing defect in the surface of a layer 1.6.13 cosmetic scratch a shallow scratch which may extend co

39、mpletely across a layer and which does not expose or damage underlying layers, or laterally displace metallization beyond the edge of the conductor forexample by mechanical deformation 1.6.14 void any defect in a layer not caused by a scratch where underlying material is visible 1.7 Interpretation R

40、eference herein to “that exhibits” shall be considered satisfied when the visual image or visual appearance of the device under examination indicates a specific condition is present. This shall not require confirmation by any other method of testing. 1.8 Alternative test methods The visual examinati

41、on requirements given below are not necessarily the only methods which can be used. However the manufacturer shall satisfy the ONS that any alternative method will give equivalent assurance otherwise the specified method shall be used. 2 Substrate and processes Low magnification 2.1 Substrate No dev

42、ice shall be acceptable that shows the following: Holes through the substrate, except through lead holes, used or unused component mounting holes, or alignment holes. Any crack that exceeds 0,125mm in length and points toward an operating portion of the circuit see Figure 1. Any chip-out that reduce

43、s any active (metallized) circuit area see Figure 2. Any crack that comes closer than 0,025 mm to an operating portion of the circuit see Figure 3. Any substrate having attached portions of another substrate that exceed the substrate dimensions allowed by the assembly drawing see Figure 4. Any subst

44、rate having a section broken out around any substrate mounting hole greater than25 % of the mounting hole circumference when designed for substrate to post attachment see Figure 5. Any crack that originates at an edge see Figure 6. 2.2 Processes 2.2.1 Conductors No device shall be acceptable that sh

45、ows the following: 1) Metallization scratches A scratch is any tearing effect, including probe marks, in the surface of the metallization. Scratch in the metallization excluding bonding pads that exposes the substrate or underlying dielectric anywhere along its length and leaves less than 50 % of th

46、e metal width undisturbed see Figure 7. Scratch in multilayered metallization that exposes the underlying metal anywhere along its length and leaves less than 50 % of the top layer metal width undisturbed see Figure 8. Scratch in the bonding pad or fillet area that exposes the underlying dielectric

47、or substrate and reduces the metallization path width connecting the bond to the interconnecting metallization to less than 50 % of the narrowest entering interconnect metallization stripe width. If two or more stripes enter a bonding pad, each shall be considered separately see Figure 9. 2) Metalli

48、zation voids Void(s) in the metallization except for wire or beam lead bonding pads that leaves less than 50 % of the metal width undisturbed seeFigure 7. Void(s) in the wire or beam lead bonding pad area that leaves an area less than twice the maximum allowable bond size undisturbed. Void(s) in the

49、 wire or beam lead bonding pad, including fillet area, that reduces the metallization path width connecting the bond to the interconnecting metallization to less than 50 % of the narrowest entering interconnect metallization stripe width seeFigure 9 NOTEIf two or more stripes enter a bonding pad, each shall be considered separately. 3) Metallization corrosion Any metallization corrosion see Figure 10. 4) Metallization adherenceEN165000-2:1996 BSI 10-1998 7 Any metallization lifting, peeling or bli