DLA SMD-5962-87597 REV B-2005 MICROCIRCUIT UNIVERSAL INTERRUPT CONTROLLER N-CHANNEL MOS MONOLITHIC SILICON《硅单块 N沟道金属氧化物半导体 万能中断控制器微型电路》.pdf

《DLA SMD-5962-87597 REV B-2005 MICROCIRCUIT UNIVERSAL INTERRUPT CONTROLLER N-CHANNEL MOS MONOLITHIC SILICON《硅单块 N沟道金属氧化物半导体 万能中断控制器微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-87597 REV B-2005 MICROCIRCUIT UNIVERSAL INTERRUPT CONTROLLER N-CHANNEL MOS MONOLITHIC SILICON《硅单块 N沟道金属氧化物半导体 万能中断控制器微型电路》.pdf（15页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add the statements to paragraphs 3.1 and 3.5.1 to allow manufacturer to meet the die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535. Update boilerplate. Editorial changes throughout. 00-03-30 Monica L. Poelking B Update boilerplat

2、e to MIL-PRF-38535 requirements. - CFS 05-08-22 Thomas M. Hess THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV SHET REV B B B B B B B B B B B B B B REV STATUS OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Ray Monnin CHECKED BY D. A. DiCenzo DEFENSE S

3、UPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY N. A. Hauck DRAWING APPROVAL DATE 87-05-01 MICROCIRCUIT, UNIVERSAL INTERRUPT CONTROLLER, N-CHANNEL MOS, MONOLITHIC SILICON SIZE A CAGE CODE 67268 5962-87597 STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR

4、USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A REVISION LEVEL B SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E414-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87597 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY

5、 CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN).

6、The complete PIN is as shown in the following example: 5962-87597 01 X X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 9519A Univer

7、sal interrupt controller 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 Dual-in-line Y CQCC1-N44 44 Square leadless chip carrier 1.2.3 Lead finish. The lead finish

8、is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range -0.5 V dc to +7 V dc Input voltage range -0.5 V dc to +7 V dc Maximum power dissipation (PD) 1.5 W 1/ Storage temperature range -65C to +150C Lead temperature (soldering, 5 seconds). +270C Thermal resist

9、ance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ). +150C 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Minimum low level input voltage (VIL). -0.5 V dc Minimum high level input voltage (VIH) . 2.0 V dc Maximum low level input voltage (

10、VIL) 0.8 V dc Maximum high level input voltage (VIH) VCCCase operating temperature range (TC) . -55C to +125C _ 1/ Must withstand the added PDdue to short circuit test (e.g., IOS). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87597 STA

11、NDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the

12、extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Me

13、thod Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.dap

14、s.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this d

15、rawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level

16、B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the m

17、anufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These mo

18、difications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. This drawing has been modified to allow the manufacturer to use the alternate die/fabrication requirements of paragra

19、ph A.3.2.2 of MIL-PRF-38535 of other alternative approved by the Qualifying Activity. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in

20、 accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth tables. The truth tables shall be as specified on figure 2. 3.2.4 Block diagram. The block diagram shall be as specified on figure 3. 3.2.5 Switching waveforms. The swit

21、ching waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. T

22、he electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87597 STANDARD MICROCIRCUIT DRAWING DEFENSE SUP

23、PLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages whe

24、re marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, app

25、endix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. For product built in accordance with A.3.2.2 of MIL-PRF-38535, or as modified in the manufacturers QM plan, the “QD” certifica

26、tion mark shall be used in place of the “Q“ or “QML“ certification mark. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to

27、 DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provid

28、ed with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufactur

29、ers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87597 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY C

30、ENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device type Group A subgroups Min Max Unit Input low voltage VILAll 1, 2,

31、3 0.8 V Input high voltage VIHAll 1, 2, 3 2.0 V Output low voltage VOL1VCC= 4.5 V, IOL= 3.2 mA All 1, 2, 3 0.40 V Output low voltage (EO only) VOL2VCC= 4.5 V, IOL= 1.0 mA All 1, 2, 3 0.40 V Output high voltage 1/ VOH1VCC= 4.5 V, IOH= -200 A All 1, 2, 3 2.4 V Output high voltage (EO only) VOH2VCC= 4.

32、5 V, IOH= -100 A All 1, 2, 3 2.4 V Output float leakage IOZVCC= 5.5 V VOUT= 5.5 V and 0.0 V Output off All 1, 2, 3 -150 +150 A Input leakage IIX1VCC= 5.5 V VIN= 5.5 V and 0.0 V All 1, 2, 3 -10 +10 A Input leakage (EI only) IIX2VCC= 5.5 V VIN= 5.5 V and 0.0 V All 1, 2, 3 -60 +10 A Power supply curren

33、t ICCVCC= 5.5 V 2/ All 1, 2, 3 200 mA Input capacitance CIN4 10 Outptut capacitance COUT 4 15 I/O capacitance CI/O TA= +25C fC= 1 MHz See 4.3.1d All 4 20 pF Functional test See 4.3.1c All 7, 8 C/ D valid and CS low to READ low tAVRLAll 9, 10, 11 0 ns C/ D valid and CS low to WRITE low tAVWLAll 9, 10

34、, 11 0 ns RIP low to PAUSE high 5/ tCLPHAll 9, 10, 11 75 375 ns RIP low to data out valid 6/ tCLQVAll 9, 10, 11 50 ns Data in valid to write high tDVWHAll 9, 10, 11 250 ns EI high to RIP low 7/ tEHCL3/ 4/ All 9, 10, 11 30 300 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduc

35、tion or networking permitted without license from IHS-,-,-SIZE A 5962-87597 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions

36、 -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device type Group A subgroups Min Max Unit Interrupt request valid to GINT valid tIVGVAll 9, 10, 11 100 800 ns Interrupt request valid to interrupt request dont care. (IREQ pulse duration) tIVIXAll 9, 10, 11 250 ns IACK high to RIP high tKH

37、CHAll 9, 10, 11 450 ns IACK high to GINT invalid tKHIHAll 9, 10, 11 1000 ns IACK high to IACK low (IACK recovery) tKHKLAll 9, 10, 11 140 ns IACK high to EO high 8/ 9/ tKHNHAll 9, 10, 11 975 ns IACK high to data out invalid tKHQXAll 9, 10, 11 20 200 ns IACK low to RIP low 7/ 10/ tKLCLAll 9, 10, 11 75

38、 650 ns IACK low to IACK high (1stIACK ) 10/ tKLKHAll 9, 10, 11 975 ns IACK low to EO low 8/ 9/ 10/ tKLNLAll 9, 10, 11 125 ns IACK low to PAUSE low 10/ tKLPLAll 9, 10, 11 25 175 ns IACK low to data out valid 6/ 10/ tKLQVAll 9, 10, 11 25 300 ns 1stIACK low to data out valid 10/ tKLQV1All 9, 10, 11 75

39、 650 ns PAUSE high to IACK low tPHKHAll 9, 10, 11 0 ns Read high to C/ D and CS dont care tRHAX3/ 4/ All 9, 10, 11 0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87597 STANDARD MICROCIRCUIT DRAWING DEF

40、ENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device type Group A subgroups Min Max Unit Read l

41、ow to data out valid tRLQVAll 9, 10, 11 300 ns Read high to data out invalid tRHQXAll 9, 10, 11 20 200 ns Read low to data out unknown tRLQXAll 9, 10, 11 35 ns Read low to read high ( RD pulse duration) tRLRHAll 9, 10, 11 300 ns Write high to C/ D and CS dont care tWHAXAll 9, 10, 11 25 ns Write high

42、 to data in dont care tWHDXAll 9, 10, 11 25 ns Write high to read or write low ( WR recovery) tWHRWAll 9, 10, 11 600 ns Write low to write high ( WR pulse duration) tWLWH3/ 4/ All 9, 10, 11 300 ns 1/ VOHspecifications do not apply to RIP , PAUSE , or GINT when active low. These outputs are open-drai

43、n and VOHlevels will be determined by external circuitry. 2/ ICCis measured in a static condition with outputs in the worst condition with all outputs unloaded. 3/ Test conditions: VIL= 0.45 V VIH= 2.4 V VOL= 0.8 V VOH= 2.0 V IOL= 3.2 mA IOH= -200 A IOL= 1.0 mA IOH= -100 A (EO only) CL= 100 pF 4/ Se

44、e figure 4. 5/ During the first IACK pulse, PAUSE will be low long enough to allow for priority resolution and will not go high until after RIP goes low (tCLPH). 6/ tKLQVapplies only to second, third, and fourth IACK pulses while RIP is low. During the first IACK pulse, data out will be valid follow

45、ing the falling edge of RIP (tCLQV). 7/ RIP is pulled low to indicate that an interrupt request has been selected. RIP cannot be pulled low until EI is high following an internal delay. tKLCLwill govern the falling edge of RIP when EI is always high or is high early in the acknowledge cycle. tEHCLwi

46、ll gevern when EI goes high later in the cycle. The rising edge of EI will be determined by the length of the preceding priority resolution chain. RIP remains low until after the rising edge of IACK pulse that transfers the last response byte for selected IREQ. 8/ Test conditions for EO assume an ou

47、tput loading of IOL= 1.0 mA and IOH= -100 A. 9/ The arrival of IACK will cause EO to go low, disabling additional circuits that may be connected to EO. If no valid interrupt is pending, EO will return high when EI is high. If a pending request is selected, EO will stay low until after the last IACK

48、pulse for that interrupt is complete and RIP goes high. 10/ CS must be high for at least 100 ns prior to IACK going low. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87597 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS CO

49、LUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Device type All Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 CS 15 PAUSE 2 WR 16 EO 3 RD 17 GINT 4 DB718 IREQ05 DB619 IREQ16 DB520 IREQ27 DB421 IREQ38 DB322 IREQ49 DB223 IREQ510 DB124 IREQ611 DB025 IREQ712 RIP 26 IACK