DLA SMD-5962-00504 REV A-2008 MICROCIRCUIT DIGITAL-LINEAR ANALOG-TO-DIGITAL CONVERTER 8-BIT 1 GSPS MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Redraw. For case outline X, change A3 dimension. - drw 08-11-19 Robert M. Heber REV SHET REV A A A SHEET 15 16 17 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Dan Wonnell CHECKED

2、 BY Raymond Monnin DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY Raymond Monnin STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 01-11-15 MICROCIRCUIT, DIGI

3、TAL-LINEAR, ANALOG-TO-DIGITAL CONVERTER, 8-BIT, 1 GSPS, MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-00504 SHEET 1 OF 17 DSCC FORM 2233 APR 97 5962-E051-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRC

4、UIT DRAWING SIZE A 5962-00504 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device cl

5、ass V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 00504 01 Q X C Fed

6、eral stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are mar

7、ked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type. The device type identifies the circuit function as follows:

8、 Device type Generic number Circuit function 01 8388B A/D converter, 8-bit, wide bandwidth, 1 giga samples per second sampling rate 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements docum

9、entation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outlines. The case outlines are as designated in MIL-STD-1835 and as

10、 follows: Outline letter Descriptive designator Terminals Package style X See figure 1 68 Quad flat pack with gull-wing leads, enhanced JCY See figure 1 68 Quad flat pack with gull-wing leads 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38

11、535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-00504 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute m

12、aximum ratings. 1/, 2/, 3/ Positive supply voltage (VCC) . GND to 6 V dc Digital negative supply voltage (DVEE) . GND to -5.7 V dc Digital positive supply voltage (VPLUSD) GND 0.3 V to 2.8 V dc Negative supply voltage (VEE) GND to 6 V dc Maximum difference between negative supply voltages (DVEEto VE

13、E) 0.3 V dc Analog input voltages (VINor VINB) . -1 V to 1 V dc Maximum difference between analog inputs (VIN- VINB) -2 V to 2 V dc Digital input voltage (VD): GORB. -0.3 V to VCC+ 0.3 V dc DRRB . VEE 0.3 V to 0.9 V dc Digital output voltage (VO) VPLUSD 3 V to VPLUSD 0.5 V dc Clock input voltage (VC

14、LKor VCLKB). -3 V to 1.5 V dc Maximum difference between clock inputs (VCLK VCLKB) -2 V to 2 V dc Junction temperature (TJ). +135C Storage temperature (TSTG) -65C to +150C Lead temperature (TLEAD). +300C Thermal resistance, junction-to-case (JC): Case outline X 1.56C/W Case outline Y 4.75C/W 1.4 Rec

15、ommended operating conditions. Positive supply voltage range (VCC) . 4.75 V to 5.25 V dc; 5 V dc typical Positive digital supply voltage (VPLUSD): ECL output compatibility. GND LVDS output compatibility. +1.4 V to +2.6 V dc; +2.4 V dc typical Negative supply voltage range (VEE, VDVEE) . -5.25 V to 4

16、.75 V dc; -5 V dc typical Differential analog input voltage (full scale, 50 differential or single-ended): VIN, VINB113 mV to 137 mV dc; 125 mV dc typical VIN- VINB. 450 mVPPto 550 mVPP; 500 mVPPtypical Clock input power level (50 single-ended clock input): PCLK, PCLKB3 dBm to 10 dBm max.; 4 dBm typ

17、ical Operating temperature range. -55C TC, TJ +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these docume

18、nts are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels m

19、ay degrade performance and affect reliability. 2/ Absolute maximum ratings are limited values, to be applied individually, while other parameters are within specified operating conditions. 3/ The use of thermal heatsink is mandatory. Provided by IHSNot for ResaleNo reproduction or networking permitt

20、ed without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-00504 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard

21、Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Ord

22、er Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and r

23、egulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The

24、modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dim

25、ensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Term

26、inal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Timing waveforms. The timing waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation param

27、eter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the

28、subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due

29、to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance

30、 with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleN

31、o reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-00504 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55 (-0/

32、+5)C TC; TJ+125 (-5/+0)C VEE= DVEE= -5 V, VCC= +5 V, VIN VINB= 500 mVpp full scale differential input, digital outputs 75 or 50 differentially terminated. Group A subgroups Device type Limits Unit unless otherwise specified Min Max Full scale input voltage VINDifferential mode 1, 2, 3 01 -125 125 mV

33、 range Single-ended input option -250 250 VINB0 V common mode voltage -125 125 Analog input capacitance CIN 4 1/ 01 3.5 pF Input bias current IIN1 1/ 01 20 A Input resistance RIN1 1/ 01 0.5 M Full power input bandwidth FPBW 4 1/ 01 1.3 GHz Small single input bandwidth SSBW 4 1/ 01 1.5 GHz Logic “0”

34、input voltage VIL1, 2, 3 01 -1.5 V Logic “1” input voltage VIH1, 2, 3 01 -1.1 V Logic “0” input current IIL1, 2, 3 01 50 A Logic “1” input current IIH1, 2, 3 01 50 A Clock input power level PCLK4 1/ 01 -2 10 dBm Clock input capacitance CCLK4 1/ 3.5 pF Differential output voltage swings VDIFF75 open

35、transmission lines, VPLUSD= 0 V 1, 2, 3 01 1.50 V 2/, 3/ 75 differentially terminated VPLUSD= 0 V 0.70 50 differentially terminated VPLUSD= 0 V 0.54 Logic “0” output voltage VOL75 open transmission lines, VPLUSD= 0 V 1 01 -1.54 V 2/, 3/ 75 differentially terminated VPLUSD= 0 V -1.34 50 differentiall

36、y terminated VPLUSD= 0 V -1.32 Logic “1” output voltage VOH75 open transmission lines, VPLUSD= 0 V 1 01 -0.88 V 2/, 3/ 75 differentially terminated VPLUSD= 0 V -1.07 50 differentially terminated VPLUSD= 0 V -1.16 Output level drift 2/, 3/ VOD1, 2, 3 01 1.6 mV/C See footnotes at end of table.Provided

37、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-00504 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continue

38、d. Test Symbol Conditions -55 (-0/+5)C TC; TJ+125 (-5/+0)C VEE= DVEE= -5 V, VCC= +5 V, VIN VINB= 500 mVpp full scale differential input, digital outputs 75 or 50 differentially terminated. Group A subgroups Device type Limits Unit unless otherwise specified Min Max Differential non linearity DNL 2/,

39、 4/ 1 01 -0.5 0.6 LSB 2, 3 -0.6 0.7 Integral non linearity INL 2/, 4/ 1 01 -1.0 1.0 LSB 2, 3 -1.2 1.2 Gain error AE2/ 1 01 -10 10 %FS 2, 3 -11 11 Input offset voltage VINOFF2/ 1 01 -26 26 mV 2, 3 -30 30 Gain error drift TCA2/ 1 1/ 01 100 150 ppm/C Offset error drift TCOFF2/ 1 1/ 01 40 60 ppm/C Posit

40、ive supply voltage, analog VCC1, 2, 3 01 4.75 5.25 V Positive supply voltage, digital VPLUSD1, 2, 3 01 1.4 2.6 V Positive supply current, analog ICC1, 2, 3 01 445 mA Positive supply current, digital IPLUSD1, 2, 3 01 145 mA Negative supply voltage VEE1, 2, 3 01 -5.25 -4.75 V Negative supply current,

41、analog AIEE1, 2, 3 01 200 mA Negative supply current, digital DIEE1, 2, 3 01 180 mA Power dissipation PD1, 2, 3 01 4.3 W Power supply rejection ratio PSRR 1 1/ 01 40 mV/V Bit error rate BER 5/ 9 1/ 01 1E-12 error/ sample ADC settling time tSVIN VINB= 400 mVPP9 1/ 01 0.5 1 ns Overvoltage recovery tim

42、e tOR 9 1/ 01 0.5 1 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-00504 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR

43、 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions -55 (-0/+5)C TC; TJ+125 (-5/+0)C VEE= DVEE= -5 V, VCC= +5 V, VIN VINB= 500 mVpp full scale differential input, digital outputs 75 or 50 differentially terminated. Group A subgroups Device type Limits Unit unless

44、otherwise specified Min Max Signal to noise and distortion ratio SINAD FS= 1 GSPS, FIN= 20 MHz 4, 5, 6 1/ 01 42 dB 2/ FS= 1 GSPS, FIN= 500 MHz 41 FS= 1 GSPS, FIN= 1000 MHz (-1 dBFS) 38 Effective number of bits ENOB FS= 1 GSPS, FIN= 20 MHz 4, 5, 6 1/ 01 7 dB 2/ FS= 1 GSPS, FIN= 500 MHz 6.6 FS= 1 GSPS

45、, FIN= 1000 MHz (-1 dBFS) 6.2 Signal to noise ratio SNR FS= 1 GSPS, FIN= 20 MHz 4, 5, 6 1/ 01 42 dB 2/ FS= 1 GSPS, FIN= 500 MHz 41 FS= 1 GSPS, FIN= 1000 MHz (-1 dBFS) 41 Total harmonic distortion THD FS= 1 GSPS, FIN= 20 MHz 4, 5, 6 1/ 01 50 dB 2/ FS= 1 GSPS, FIN= 500 MHz 46 FS= 1 GSPS, FIN= 1000 MHz

46、 (-1 dBFS) 42 Spurious free dynamic range SFDR FS= 1 GSPS, FIN= 20 MHz 4, 5, 6 1/ 01 -52 dBc 2/ FS= 1 GSPS, FIN= 500 MHz -47 FS= 1 GSPS, FIN= 1000 MHz (-1 dBFS) -42 FS= 1 GSPS, FIN= 1000 MHz (-3 dBFS) -45 Two-tone intermodulation distortion 2/ IMD FIN1= 489 MHzFS= 1 GSPS FIN2= 490 MHzFS= 1 GSPS 4, 5

47、, 6 1/ 01 -47 dBc Maximum clock frequency FSSee figure 4, 6/ 4, 5, 6 1/ 01 1 1.4 GSPS Minimum clock frequency FSSee figure 4, 7/ 4, 5, 6 1/ 01 10 50 MSPS Maximum clock pulse width (high) tC1See figure 4 4, 5, 6 1/ 01 0.28 50 ns Maximum clock pulse width (low) tC2See figure 4 4, 5, 6 1/ 01 0.35 50 ns

48、 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-00504 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions -55 (-0/+5)C TC; TJ+125 (-5/+0)C VEE= DVEE= -5 V, VCC= +5 V, VIN VINB= 500 mVpp full scale differential input, digital outputs 75 o