DLA DSCC-VID-V62 12619-2012 MICROCIRCUIT LINEAR OPERATIONAL AMPLIFIER LOW POWER PRECISION MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original da
2、te of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, LINEAR, OPERATIONAL AMPLIFIER, LOW POWER, PRECISION, MONOLITHIC SILICON 12-07-31 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12619 REV PAGE 1 OF 11 AMSC N/A 5962-V074-12 Provided by IHSNot for ResaleNo r
3、eproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12619 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low power precision operational amplifier microcirc
4、uit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/1
5、2619 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 OPA211-EP Low power precision operational amplifier 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter N
6、umber of pins JEDEC PUB 95 Package style X 8 MO-187 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash pa
7、lladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage (VS= +V - -V) 40 V Input voltage (VIN) -V 0.5 V to +V + 0.5 V Input current (any pin except power supply pins) . 10 mA Output short circuit . Continuous 2/ Storage temperature range (TSTG) -65C to +150C Junction temperature range (TJ) 2
8、00C Electrostatic discharge (ESD) ratings: Human body model (HBM) . 3000 V Charged device model (CDM) 1000 V 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any
9、 other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Short circuit to VS/2 (ground in symmetrical dual supply setups), one amplifier per package. Provided
10、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12619 REV PAGE 3 1.4 Recommended operating conditions. 3/ Supply voltage 2.25 V to 18 V Operating free-air temperature range (TA) -55
11、C to +125C 1.5 Thermal characteristics. Thermal metric Symbol Case X Unit Thermal resistance, junction-to-ambient 4/ JA184.9 C/W Thermal resistance, junction-to-case (top) 5/ JC(TOP)71.2 C/W Thermal resistance, junction-to-board 6/ JB104.9 C/W Characterization parameter, junction-to-top 7/ JT11.5 C/
12、W Characterization parameter, junction-to-board 8/ JB103.4 C/W _ 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ The
13、thermal resistance, junction-to-ambient under natural convection is obtained in a simulation on a JEDEC standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 5/ The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the pac
14、kage top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 6/ The thermal resistance, junction-to-board is obtained by simulating in an environment with a ring cold plate fixture to control the printed circuit board (PCB) temperature, as
15、described in JESD51-8. 7/ Characterization parameter, junction-to-top (JT) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 8/ Characterization parameter, junction-
16、to-board (JB) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA
17、 LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12619 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices EIA/JESD51-2a - Integrated Circuits Thermal Test Method Environment Co
18、nditions Natural Convection (Still Air) EIA/JEDEC 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages EIA/JESD51-8 - Integrated Circuits Thermal Test Method Environment Conditions Junction-to-Board (Applications for copies should be addressed to the Electronic Ind
19、ustries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) ANSI SEMI STANDARD G30-88 - Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Instit
20、ute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manuf
21、acturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating condit
22、ions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2
23、 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12619 REV PAGE 5 TABLE I.
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