DLA DSCC-VID-V62 12619-2012 MICROCIRCUIT LINEAR OPERATIONAL AMPLIFIER LOW POWER PRECISION MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original da

2、te of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, LINEAR, OPERATIONAL AMPLIFIER, LOW POWER, PRECISION, MONOLITHIC SILICON 12-07-31 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12619 REV PAGE 1 OF 11 AMSC N/A 5962-V074-12 Provided by IHSNot for ResaleNo r

3、eproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12619 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low power precision operational amplifier microcirc

4、uit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/1

5、2619 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 OPA211-EP Low power precision operational amplifier 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter N

6、umber of pins JEDEC PUB 95 Package style X 8 MO-187 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash pa

7、lladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage (VS= +V - -V) 40 V Input voltage (VIN) -V 0.5 V to +V + 0.5 V Input current (any pin except power supply pins) . 10 mA Output short circuit . Continuous 2/ Storage temperature range (TSTG) -65C to +150C Junction temperature range (TJ) 2

8、00C Electrostatic discharge (ESD) ratings: Human body model (HBM) . 3000 V Charged device model (CDM) 1000 V 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any

9、 other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Short circuit to VS/2 (ground in symmetrical dual supply setups), one amplifier per package. Provided

10、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12619 REV PAGE 3 1.4 Recommended operating conditions. 3/ Supply voltage 2.25 V to 18 V Operating free-air temperature range (TA) -55

11、C to +125C 1.5 Thermal characteristics. Thermal metric Symbol Case X Unit Thermal resistance, junction-to-ambient 4/ JA184.9 C/W Thermal resistance, junction-to-case (top) 5/ JC(TOP)71.2 C/W Thermal resistance, junction-to-board 6/ JB104.9 C/W Characterization parameter, junction-to-top 7/ JT11.5 C/

12、W Characterization parameter, junction-to-board 8/ JB103.4 C/W _ 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ The

13、thermal resistance, junction-to-ambient under natural convection is obtained in a simulation on a JEDEC standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 5/ The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the pac

14、kage top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 6/ The thermal resistance, junction-to-board is obtained by simulating in an environment with a ring cold plate fixture to control the printed circuit board (PCB) temperature, as

15、described in JESD51-8. 7/ Characterization parameter, junction-to-top (JT) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 8/ Characterization parameter, junction-

16、to-board (JB) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA

17、 LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12619 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices EIA/JESD51-2a - Integrated Circuits Thermal Test Method Environment Co

18、nditions Natural Convection (Still Air) EIA/JEDEC 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages EIA/JESD51-8 - Integrated Circuits Thermal Test Method Environment Conditions Junction-to-Board (Applications for copies should be addressed to the Electronic Ind

19、ustries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) ANSI SEMI STANDARD G30-88 - Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Instit

20、ute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manuf

21、acturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating condit

22、ions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2

23、 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12619 REV PAGE 5 TABLE I.

24、Electrical performance characteristics. 1/ Test Symbol Conditions 2/ VS= 2.25 V to 18 V unless otherwise specifiedTemperature, TADevice type Limits Unit Min Max Offset voltage section. Input offset voltage VOSVS= 15 V +25C 01 100 V -55C to +125C 180 Input offset voltage drift VOS/ T -55C to +125C 01

25、 0.35 typical V / C Input offset voltage versus power supply PSRR VS= 2.25 V to 18 V +25C 01 0.5 V/V -55C to +125C 3 Input bias current section. Input bias current IBVCM= 0 V -55C to +125C 01 200 nA Offset current IOSVCM= 0 V -55C to +125C 01 150 nA Noise section. Input voltage noise enf = 0.1 Hz to

26、 10 Hz +25C 01 80 typical nVPPInput voltage noise density enf = 10 Hz +25C 01 2 typical nV / Hz f = 100 Hz 1.4 typical f = 1 kHz 1.1 typical Input current noise density Inf = 10 Hz +25C 01 3.2 typical nV / Hz f = 1 kHz 1.7 typical Input voltage range. Common mode voltage range VCMVS 5 V +25C 01 (-V)

27、 + 1.8 (+V) 1.4 V VS 5 V (-V) + 2 (+V) 1.4 Common mode rejection ratio CMRR VS 5 V, (-V) + 2 V VCM(+V) -2 V -55C to +125C 01 114 dB VS 5 V, (-V) + 2 V VCM(+V) -2 V 108 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA

28、 LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12619 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ VS= 2.25 V to 18 V unless otherwise specifiedTemperature, TADevice type Limits Unit Min Max Input impedance. Differential

29、 3/ +25C 01 20k | 8 typical |pF Common mode 3/ +25C 01 109| 2 typical |pF Open loop gain. Open loop voltage gain AOL(-V) + 0.2 V VO (+V) 0.2 V, RL= 10 k -55C to +125C 01 114 dB (-V) + 0.6 V VO (+V) 0.6 V, RL= 600 +25C 110 Open loop gain over temperature AOL(-V) + 0.6 V VO (+V) 0.6 V, IO 15 mA -55C t

30、o +125C 01 110 dB (-V) + 0.6 V VO (+V) 0.6 V, 15 mA IO 30 mA 103 Frequency response. Gain bandwidth product GBW G = 100 +25C 01 80 typical MHz G = 1 45 typical Slew rate SR +25C 01 27 typical V/s Settling time, 0.01% tSVS= 15 V, G = -1, 10 V step, CL= 100 pF +25C 01 400 typical ns Settling time, 0.0

31、015% (16 bit) tSVS= 15 V, G = -1, 10 V step, CL= 100 pF +25C 01 700 typical ns Overload recovery time G = -10 +25C 01 500 typical ns Total harmonic distortion + noise THD + N G = +1, f = 1 kHz, VO= 3 VRMS, RL= 600 +25C 01 0.000015 typical % Output. Voltage output VOUTRL= 10 k, AOL 114 dB -55C to +12

32、5C 01 (-V) + 0.2 (+V) 0.2 V RL= 600 , AOL 110 dB +25C (-V) + 0.6 (+V) 0.6 IO 15 mA, AOL 110 dB -55C to +125C (-V) + 0.6 (+V) 0.6 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE

33、A CODE IDENT NO. 16236 DWG NO. V62/12619 REV PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ VS= 2.25 V to 18 V unless otherwise specifiedTemperature, TADevice type Limits Unit Min Max Output continued. Short circuit current ISC+25C 01 +30/-45 typical m

34、A Open loop output impedance ZOf = 1 MHz +25C 01 5 typical Shutdown. Shutdown pin input 4/ voltage Device disabled (shutdown) +25C 01 (+V) 0.35 V Device enabled (+V) - 3 Shutdown pin leakage current +25C 01 1 typical A Turn on time +25C 01 2 typical s Turn off time +25C 01 3 typical s Shutdown curre

35、nt Shutdown (disabled) +25C 01 20 A Power supply. Specified voltage VS+25C 01 2.25 18 V Quiescent current (per channel) IQIOUT= 0 A +25C 01 4.5 mA -55C to +125C 6 Temperature range. Operating range TA01 -55 +125 C Thermal resistance JA +25C 01 200 typical C/W 1/ Testing and other quality control tec

36、hniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product perform

37、ance is assured by characterization and/or design. 2/ Unless otherwise specified, RL= 10 k connected to midsupply and VCM= VOUT= midsupply. 3/ The | symbolizes that the input impedance is being represented as the resistance value is in parallel with the capacitance. 4/ When disabled, the output assu

38、mes a high impedance state. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12619 REV PAGE 8 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or n

39、etworking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12619 REV PAGE 9 Case X Symbol Dimensions Inches Millimeters Min Max Min Max A - 0.043 - 1.10 A1 0.001 0.006 0.05 0.15 b 0.010 0.014 0.25 0.38 c 0.005 0.009 0.13 0.23 D 0.114

40、 0.122 2.90 3.10 E 0.114 0.122 2.90 3.10 E1 0.187 0.199 4.75 5.05 e 0.026 BSC 0.65 BSC L 0.015 0.027 0.40 0.70 NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. For dimension D, body length does not include mold flash, protrusion, or gate burrs. Mold f

41、lash, protrusion, or gate burrs shall not exceed 0.15 mm (0.006 inch) per end. 3. For dimension E, body width does not include interlead flash. Interlead flash shall not exceed 0.50 mm (0.019 inch) per side. 4. Falls with JEDEC MO-187-AA, except interlead flash. FIGURE 1. Case outline - Continued. P

42、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12619 REV PAGE 10 Device type 01 Case outline X Terminal number Terminal symbol 1 NC SEE NOTE 1 2 -INPUT 3 +INPUT 4 -V 5 NC SE

43、E NOTE 1 6 OUTPUT 7 +V 8 SHUTDOWN SEE NOTE 2 NOTES: 1. NC denotes no internal connection. 2. Shutdown function: Device enabled: (-V) VSHUTDOWN (+V) 3 V Device disabled: VSHUTDOWN (+V) 0.35 V FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without

44、license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12619 REV PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Su

45、ch procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacture

46、rs standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manu

47、facturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http: