DLA DSCC-VID-V62 12617 REV A-2012 MICROCIRCUIT DIGITAL LOW CAPACITANCE LOW CHARGE INJECTION 5 V +12 V iCMOS QUAD SPST SWITCHES MONOLITHIC SILICON.pdf
《DLA DSCC-VID-V62 12617 REV A-2012 MICROCIRCUIT DIGITAL LOW CAPACITANCE LOW CHARGE INJECTION 5 V +12 V iCMOS QUAD SPST SWITCHES MONOLITHIC SILICON.pdf》由会员分享,可在线阅读,更多相关《DLA DSCC-VID-V62 12617 REV A-2012 MICROCIRCUIT DIGITAL LOW CAPACITANCE LOW CHARGE INJECTION 5 V +12 V iCMOS QUAD SPST SWITCHES MONOLITHIC SILICON.pdf(13页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Correct the operating temperature range in section 1.3 and the pin out in section 1.2.2. - phn 12-09-20 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A A PAGE 1 2 3
2、 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, LOW CAPACITANCE, LOW CHARGE INJECTION, 15 V/+12 V iCMOS QUAD SPST SWITCHES, MONOL
3、ITHIC SILICON 12-04-09 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12617 REV A PAGE 1 OF 13 AMSC N/A 5962-V104-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236
4、 DWG NO. V62/12617 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low capacitance, low charge injection, 15 V/+12 V iCMOS quad SPST switches microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrat
5、ive Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12617 - 01 X B Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See
6、 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 ADG1212-EP Low capacitance, low charge injection, 15 V/+12 V iCMOS quad SPST switches 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 JEDEC MO-153-AB
7、Lead thin Shrink Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot
8、for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12617 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ VDDto VSS35 V VDDto GND . -0.3 V to +35 V VSSto GND +0.3 V to -25 V Analog inputs VSS- 0.3 V
9、 to VDD+ 0.3 V 2/ or 30 mA which ever occurs first Digital inputs GND - 0.3 V to VDD+ 0.3 V 2/ or 30 mA which ever occurs first Peak current, S or D 100 mA (pulsed at 1 ms, 10% duty cycles max) Continuous current per channel, S or D 25 mA Operating temperature range . -55C to +125C Storage temperatu
10、re range . -65C to 150C Junction temperature 150C 16 lead TSSOP, JAThermal impedance (4 layer board) . 112C/W Lead temperature, soldering . As per JEDEC J-STD 020 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices
11、 J-STD-020 Joint IPC/JEDEC standard for moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington
12、, VA 22201.) 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implie
13、d. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ Over voltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. Provided by IHSNot for ResaleNo reproduction or networking permitted without li
14、cense from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12617 REV A PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or
15、 logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performa
16、nce characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Termina
17、l connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 Truth table. The truth table shall be as shown in figure 4. 3.5.5 Functional block diagram. The functional block diagram shall be as shown in fig
18、ure 5. 3.5.6 Off leakage. The off leakage shall be as shown in figure 6. 3.5.7 On leakage. The on leakage shall be as shown in figure 7. 3.5.8 Off Isolation. The Off isolation shall be as shown in figure 8. 3.5.9 Channel-to-channel crosstalk. The channel-to-channel crosstalk shall be as shown in fig
19、ure 9. 3.5.10 On Resistance. The on resistance shall be as shown in figure 10. 3.5.11 Bandwidth. The bandwidth shall be as shown in figure 11. 3.5.12 THD + Noise. The THD + Noise shall be as shown in figure 12. 3.5.13 Switching times. The switching times shall be as shown in figure 13. 3.5.14 Charge
20、 injection. The charge injection shall be as shown in figure 14. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12617 REV A PAGE 5 TABLE I. Electrical performance character
21、istics. 1/ Test Symbol Conditions 2/ Limits Unit 25C -40C to +85C -40C to +125C Min Max Min Max Min Max Analog switch Analog signal range VDDto VSSV On Resistance RONVS= 10 V, IS= -1 mA See Figure 10 120 TYP VDD= +13.5 V, VSS= -13.5 V 190 230 260 On Resistance match between channel RONVS= 10 V, IS=
22、-1 mA 2.5 TYP 6 10 11 On Resistance flatness RFLAT(ON)VS= -5V/0 V/+V; IS= -1 mA 20 TYP 57 72 79 Leakage currents (VDD= +16.5 V, VSS= -16.5 V) Source off leakage IS(Off)VS= 10 V, VD= 10 V See Figure 6 0.02 TYP nA 0.1 0.6 1 Drain off leakage ID(Off)VS= 10 V, VD= 10 V See Figure 6 0.02 TYP 0.1 0.6 1 Ch
23、annel on leakage ID, IS(On)VS= VD= 10 V See Figure 7 0.02 TYP 0.1 0.6 1 Digital inputs Input high voltage VINH2.0 V Input low voltage VINL0.8 Input current IINLor IINH0.005 TYP 0.1 A Digital input capacitance CIN2.5 TYP pF Dynamic characteristics 3/ tONRL= 300 , CL= 35 pF, VS= 10 V; See Figure 13 65
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