DLA DSCC-VID-V62 12615 REV A-2012 MICROCIRCUIT DIGITAL EXTREME TEMPERATURE SINGLE PORT 10 100 MB S ETHERNET PHYSICAL LAYER TRANSCEIVER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Correct maximum operating junction temperature (TJ) to 150C, in section 1.3.-phn. 12-12-14 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV A A A A A A A A A A A A PAGE 18 19 20 21 22 23 24 25 26 27 28 29 REV STATUS OF

2、 PAGES REV A A A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, EX

3、TREME TEMPERATURE SINGLE PORT 10/100 MB/S ETHERNET PHYSICAL LAYER TRANSCEIVER, MONOLITHIC SILICON 12-11-06 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12615 REV A PAGE 1 OF 29 AMSC N/A 5962-V033-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without l

4、icense from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12615 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance extreme temperature single port 10/100 Mb/s Ethernet physical layer transceiver microcircuit,

5、with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12615

6、- 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 DP83848-EP Extreme temperature single port 10/100 Mb/s Ethernet physical layer transceiver 1.2.2 Case outline(s). The case outlines are as sp

7、ecified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 48 MS-026 Plastic Quad Flatpack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold

8、plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12615 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage, (VCC) .

9、-0.5 V to 4.2 V DC input voltage (VIN) -0.5 V to VCC+ 0.5 V DC output voltage (VOUT) -0.5 V to VCC+ 0.5 V Storage temperature (TSTG) -65C to +150C Operating junction temperature (TJ) . -55C to +150C Lead temperature (TL) (Soldering, 10 sec.) 260C ESD rating (RZAP= 1.5 k, CZAP= 100 pF) 4.0 kV 1.4 Rec

10、ommended operating conditions. 2/ Supply voltage, (VCC) . 3.0 V to 3.6 V Operating free air temperature, (TA) . -55C to +125C 3/ Power dissipation (PD) . 267 mW 1.5 Thermal characteristics. Thermal metric Case outline X Units Junction to ambient thermal resistance, JA4/ 35.74 C/W Junction to case (t

11、op) thermal resistance, JCtop5/ 21.8 Junction to board thermal resistance, JB6/ 19.5 Junction to top characterization parameter, JT7/ 1.2 Junction to board characterization parameter, JB8/ 19.4 Junction to case (bottom) thermal resistance, JCbot9/ 3.2 1/ Stresses beyond those listed under “absolute

12、maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended

13、 periods may affect device reliability. 2/ Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. 3/ Provided that thermal pad is soldered down. 4/ The junction to ambient t

14、hermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-k-board, as specified in JESD51-7, in an environment described in JESD51-2a. 5/ The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified

15、JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 6/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 7/ The junction to top

16、characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 8/ The junction to board characterization parameter, JB, estimates the junction tem

17、perature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 9/ The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specified JEDE

18、C- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12615 REV A PAGE 4 2. APPLICAB

19、LE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Sur

20、face Mount Packages JESD51-8 Junction-to-board thermal resistance Theta-JB or RJB(Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) AMERICAN NATIONAL STANDARDS INSTITUTE (A

21、NSI) STANDARD ANSI SEMI STANDARD G30-88 - Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floo

22、r, Washington, DC 20036 or online at http:/www.ansi.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional

23、) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and tabl

24、e I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown

25、in figure 2. 3.5.3 Device block diagram. The device block diagram shall be as shown in figure 3. 3.5.4 Power up timing. The power up timing shall be as shown in figure 4. 3.5.5 Reset timing. The reset timing shall be as shown in figure 5. 3.5.6 MII serial management timing. The MII serial management

26、 timing shall be as shown in figure 6. 3.5.7 100 Mb/s MII transmit timing. The 100 Mb/s MII transmit timing shall be as shown in figure 7. 3.5.8 100 Mb/s MII receive timing. The 100 Mb/s MII receive timing shall be as shown in figure 8. Provided by IHSNot for ResaleNo reproduction or networking perm

27、itted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12615 REV A PAGE 5 3.5.9 100BASE-TX transmit packet latency timing. The 100BASE-TX transmit packet latency timing shall be as shown in figure 9. 3.5.10 100BASE-TX transmit packet deasserti

28、on timing. The 100BASE-TX transmit packet deassertion timing shall be as shown in figure 10. 3.5.11 100BASE-TX transmit packet timing (tR/F & Jitter). The 100BASE-TX transmit packet timing (tR/F & Jitter) shall be as shown in figure 11. 3.5.12 100BASE-TX receive packet latency timing. The 100BASE-TX

29、 receive packet latency timing shall be as shown in figure 12. 3.5.13 100BASE-TX receive packet deassertion timing. The 100BASE-TX receive packet deassertion timing shall be as shown in figure 13. 3.5.14 10 Mb/s MII transmit timing. The 10 Mb/s MII transmit timing shall be as shown in figure 14. 3.5

30、.15 10 Mb/s MII receive timing. The 10 Mb/s MII receive timing shall be as shown in figure 15. 3.5.16 10 Mb/s serial mode transmit timing. The 10 Mb/s serial mode transmit timing shall be as shown in figure 16. 3.5.17 10 Mb/s serial mode receive timing. The 10 Mb/s serial mode receive timing shall b

31、e as shown in figure 17. 3.5.18 10BASE-T transmit timing (Start of packet). The 10BASE-T transmit timing (Start of packet) shall be as shown in figure 18. 3.5.19 10BASE-T transmit timing (End of packet). The 10BASE-T transmit timing (End of packet) shall be as shown in figure 19. 3.5.20 10BASE-T rec

32、eive timing (Start of packet). The 10BASE-T receive timing (Start of packet) shall be as shown in figure 20. 3.5.21 10BASE-T receive timing (End of packet). The 10BASE-T receive timing (End of packet) shall be as shown in figure 21. 3.5.22 10 Mb/s heartbeat timing. The 10 Mb/s heartbeat timing shall

33、 be as shown in figure 22. 3.5.23 10 Mb/s Jabber timing. The 10 Mb/s Jabber timing shall be as shown in figure 23. 3.5.24 10BASE-T normal link pulse timing. The 10BASE-T normal link pulse timing shall be as shown in figure 24. 3.5.25 Auto-Negotiation Fast Link Pulse (FLP) timing. The auto-negotiatio

34、n Fast Link Pulse (FLP) timing shall be as shown in figure 25. 3.5.26 100BASE-TX signal detect timing. The 100BASE-TX signal detect timing shall be as shown in figure 26. 3.5.27 100 Mb/s internal loopback timing. The 100 Mb/s internal loopback timing shall be as shown in figure 27. 3.5.28 10 Mb/s in

35、ternal loopback timing. The 10 Mb/s internal loopback timing shall be as shown in figure 28. 3.5.29 RMII transmit timing. The RMII transmit timing shall be as shown in figure 29. 3.5.30 RMII receive timing. The RMII receive timing shall be as shown in figure 30. 3.5.31 Isolation timing. The Isolatio

36、n timing shall be as shown in figure 31. 3.5.32 25 MHz_OUT timing. The 25 MHz_OUT timing shall be as shown in figure 32. 3.5.33 100 Mb/s X1 to TX_CLK timing. The 100 Mb/s X1 to TX_CLK timing shall be as shown in figure 33. 3.5.34 100BASE-TX transmit block diagram. The 100BASE-TX transmit block diagr

37、am shall be as shown in figure 34. 3.5.35 100BASE-TX receive block diagram. The 100BASE-TX receive block diagram shall be as shown in figure 35. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO

38、. 16236 DWG NO. V62/12615 REV A PAGE 6 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Limits Unit Min Max DC SPECIFICATIONS Input high voltage VIHNominal VCC2.0 V Input low voltage VIL0.8 V Input high current IIHVIN= VCC10 A Input low current IILVIN= GND 10 A Output lo

39、w voltage VOLIOL= 4 mA 0.4 V Output high voltage VOHIOH = -4 mA VCC 0.5 V Tri state leakage IOZVOUT= VCCor GND 10 A 100M transmit voltage VTPTD_1000.89 1.15 V 100M transmit voltage symmetry VTPTDsym2 % 10M transmit voltage VTPTD_102.17 2.8 V CMOS input capacitance CIN15 TYP pF CMOS output capacitanc

40、e COUT15 TYP 100Base-TX signal detect turn-on threshold SDTHon1000 mv diff pk-pk 100Base-TX signal detect turn-off threshold SDTHoff200 mv diff pk-pk 10Base T receive threshold VTH1585 mV 100Base TX (Full duplex) Idd10081 TYP mA 10Base TX (Full duplex) Idd1092 TYP Power down mode Idd14 TYP See footn

41、ote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12615 REV A PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Conditions 2/ Li

42、mits Unit Min Max AC SPECIFICATIONS Power up timing See Figure 4. T2.1.1 Post power up stabilization time prior to MDC preamble for register accesses MDIO is pulled high for 32 bit serial management initialization X1 clock must be stable for a min. of 167 ms at power up 167 ms T2.1.2 Hardware config

43、uration latch in time from power up Hardware configuration pins are described in the manufacturer data. X1 clock must be stable for a min. of 167 ms at power up 167 ms T2.1.3 Hardware configuration pins transition to output drivers 50 TYP ns Reset timing 3/ See Figure 5. T2.2.1 Post reset stabilizat

44、ion time prior to MDC preamble for register accesses MDIO is pulled high for 32 bit serial management initialization 3 TYP s T2.2.2 Hardware configuration latch in time from deassertion of RESET (either soft or hard) Hardware configuration pins are described in the manufacturer data 3 TYP s T2.2.3 H

45、ardware configuration pins transition to output drivers 50 TYP ns T2.2.4 RESET pulse width X1 clock must be stable for a min. of 1 s during RESET pulse low time 1 s MII serial management timing See Figure 6. T2.3.1 MDC to MDIO (output) delay time 0 30 ns T2.3.2 MDIO (input) to MDC setup time 10 ns T

46、2.3.3 MDIO (input) to MDC hold time 10 ns T2.3.4 MDC frequency 25 MHz 100 Mb/s MII transmit timing See Figure 7. T2.4.1 TX_CLK high/low time 100 Mb/s Normal mode 16 24 ns T2.4.2 TXD3:0, TX_EN data setup to TX_CLK 100 Mb/s Normal mode 9.70 ns T2.4.3 TXD3:0, TX_EN data hold from TX_CLK 100 Mb/s Normal

47、 mode 0 ns 100 Mb/s MII receive timing 4/ See Figure 8. T2.5.1 RX_CLK high/low time 100 Mb/s Normal mode 16 24 ns T2.5.2 RX_CLK to RXD3:0, RX_DV, RX_ER delay 100 Mb/s Normal mode 10 30 ns 100 Base-TX transmit packet latency timing 5/ See Figure 9. T2.6.1 TX_CLK to PMD output pair latency 100 Mb/s No

48、rmal mode 6 TYP bits 100 Base-TX transmit packet deassertion timing 6/ See Figure 10. T2.7.1 TX_CLK to PMD output pair deassertion 100 Mb/s Normal mode 6 TYP bits See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12615 REV A PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1