DLA DSCC-VID-V62 09632-2010 MICROCIRCUIT DIGITAL-LINEAR MICROPROCESSOR SUPERVISORY CIRCUITS MONOLITHIC SILICON.pdf

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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY MM DD

2、CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL-LINEAR, MICROPROCESSOR SUPERVISORY CIRCUITS, MONOLITHIC SILICON 10-03-02 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09632 REV PAGE 1 OF 12 AMSC N/A 5962-V012-10 Provided by IHSNot for ResaleNo reproduction or networking pe

3、rmitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09632 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a microprocessor supervisory circuit, with an operating temperature range of -55C to +12

4、5C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09632 - 01 X B Drawing Device type Case outline Lead fin

5、ish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 MAX691A Microprocessor supervisory circuits 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 JEDEC MS012 Small o

6、utline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networ

7、king permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09632 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Terminal voltage (with respect to GND) VCC-0.3 V to +6.0 V VBATT. -0.3 V to +6.0 V All other inputs -0.3 V to (VOUT+ 0.

8、3 V) Input current: VCCpeak . 1.0 A VCCcontinuous 250 mA VBATTpeak . 250 mA VBATTcontinuous . 25 mA GND, BATT ON 100 mA All other outputs 25 mA Junction temperature (TJ) 150C Operating temperature range . -55C to +125C Storage temperature range -65C to 150C Lead temperature (soldering , 10 sec) . +3

9、00C Electro Static Discharge (ESD) Human Body Model (HBM) . 2000 V Class . 1C Moisture Sensitivity Level (MSL) Level 1 1.4 Thermal data table. 2/ Case outline letter X X Units PC Board Single Layer Multi-Layer 2/ Power dissipation (PD), maximum at +70C 696 1067 mW Power dissipation (PD) derating abo

10、ve +70C 8.7 13.3 mW/C Thermal resistance, junction to case (JC) 32 24 C/W Thermal resistance, junction to ambient (JA) 115 75 C/W 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface

11、 Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are s

12、tress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Package thermal resistances

13、 were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to manufacturers website. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE S

14、UPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09632 REV PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 ident

15、ifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics

16、are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The t

17、erminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as shown in figure 3. 3.5.4 Reset and chip enable timing. The reset and chip enable timing shall be as shown in figure 4. 3.5.5 CE propagation delay test circuit. The CE propagation delay test circuit

18、shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09632 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Con

19、ditions Device type: All 2/ Limits Unit Min Max Operating voltage range, VCC, VBATT 3/ 0 5.5 V VOUToutput VCC= 4.5 V IOUT= 25 mA VCC 0.05 V IOUT= 250 mA VCC 0.40 VCCto VOUTON resistance VCC= 4.5 V 1.6 VOUTin battery-backup mode VBATT = 4.5 V, IOUT= 20 mA VBATT 0.3 V VBATT = 2.8 V, IOUT= 10 mA VBATT

20、0.25 VBATT = 2.0 V, IOUT= 5 mA VBATT 0.15 VBATT to VOUTON resistance VBATT = 4.5 V 15 VBATT = 2.8 V 25 VBATT = 2.0 V 30 Supply current in normal operating mode (excludes IOUT) VCC VBATT 1 V 100 A Supply current in battery backup mode (excludes IOUT) 4/ VCC VBATT 1.2 V, VBATT = 2.8 V TA= 25C 1 A TA=

21、-55C to +125C 5 VBATT standby current 5/ VBATT + 0.2 V VCCTA= 25C -0.1 0.02 A TA= -55C to +125C -1.0 0.02Battery switchover threshold Power up VBATT + 0.3 TYP V Power down VBATT 0.3 TYP V Battery switchover hysteresis 60 TYP mV BATT ON output low voltage ISINK= 3.2 mA 0.4 V ISINK= 25 mA 1.5 BATT ON

22、output short circuit current Sink current 60 TYP mA Source current 1 100 A Reset and watchdog timer Reset threshold voltage 4.50 4.75 V Reset threshold hysteresis 15 TYP mV VCCto RESET delay Power down 80 TYP s LOWLINE to RESET delay 800 TYP ns Reset active timeout period, internal oscillator Power-

23、up 140 280 ms Reset active timeout period , external clock 6/ Power-up 2048 TYP Clock cycles Watchdog timeout period, internal oscillator Long period 1.0 2.25 sec Short period 70 140 ms Watchdog timeout period, external clock 6/ Long period 4096 TYP Clock cycles Short period 1024 TYP See footnotes a

24、t end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09632 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Condit

25、ions Device type: All 2/ Limits Unit Min Max Reset and watchdog timer (continued) Minimum watchdog input pulse width VIL= 0.8 V, VIH= 0.75 x VCC100 ns RESET output voltage ISINK= 50 A, VCC= 1 V, VBATT = 0 V, VCCfalling 0.3 V ISINK= 3.2 mA, VCC= 4.25 V 0.4 ISOURCE= 1.6 mA, VCC= 5 V 3.5 RESET output s

26、hort circuit current Output source current 20 mA RESET output voltage low 7/ ISINK= 3.2 mA 0.1 V LOWLINE output voltage ISINK= 3.2 mA, VCC= 4.25 V 0.4 V ISOURCE= 1 A, VCC= 5 V 3.5 LOWLINE output short circuit current Output source current 1 100 A WDO output voltage ISINK= 3.2 mA, 0.4 V ISOURCE= 500

27、A, VCC= 5 V 3.5 WDO output short circuit current Output source current 10 mA WDI threshold voltage 8/ VIH0.75 x VCCV VIL0.8WDI input current WDI = 0 V -50 A WDI = VOUT50Power fail comparator PFI input threshold VCC= 5 V 1.2 1.3 V PFI leakage current 25 nA PFO output voltage ISINK= 3.2 mA 0.4 V ISOUR

28、CE= 1 A, VCC= 5 V 3.5 PFO output short circuit current Output source current 1 100 A PFI to PFO delay VIN= -20 mV, VOD= 15 mV 25 TYP s VIN= 20 mV, VOD= 15 mV 60 TYP Chip enable gating CE IN leakage current Disable mode 1 A CE IN to CE OUT resistance 9/ Enable mode 150 CE OUT short circuit current (R

29、eset active) Disable mode, CE OUT = 0 V 0.1 2.0 mA CE IN to CE OUT propagation delay 10/ 50 source impedance driver, CLOAD= 50 pF 10 ns CE OUT output voltage high (Reset active) VCC= 5 V, IOUT= -100 A 3.5 V VCC= 0 V, VBATT = 2.8 V, IOUT= 1 A 2.7 RESET to CE OUT delay Power down 12 TYP s See footnote

30、s at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09632 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Con

31、ditions Device type: All 2/ Limits Unit Min Max Internal oscillator OSC IN leakage current OSC SEL = 0 V 5 A OSC IN input pullup current OSC SEL = VOUT or floating, OSC IN = 0 V 100 A OSC SEL input pullup current OSC SEL = 0 V 100 A OSC IN frequency range OSC SEL = 0 V 50 TYP kHz OSC IN external osc

32、illator threshold voltage VIH OUT 0.3 V VIL2.0OSC Infrequency with external capacitor OSC SEL = 0 V, COSC= 47 pF 100 TYP kHz 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not nec

33、essarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ VCC= +4.75 V to +5.5 V, VBATT = 2.8 V, TA= -55C to 125C (unless otherwise noted).

34、 3/ Either VCCor VBATT can go to 0 V, if the other is greater than 2.0 V. 4/ The supply current drawn by this device from the battery excluding IOUTtypically goes to 10 A when: (VBATT 1 V) VCC VBATT. In most applications, this is a brief period as VCCfalls through this region. 5/ “+” = battery disch

35、arging current, “-“ = battery charging current. 6/ Although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and do not vary with process or temperature. 7/ RESET is an open drain output and sinks current only. 8/ WDI is internally connecte

36、d to a voltage divider between VOUT and GND. If unconnected, WDI is driven to 1.6 V (TYP), disabling the watchdog function. 9/ The chip enable resistance is tested with VCC= +4.75 V. CE IN = CE OUT = VCC/2. 10/ The chip enable propagation delay is measured from 50% point at CE IN to the 50% point at

37、 CE OUT. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09632 REV PAGE 8 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min

38、 Max Min Max A .053 .069 1.35 1.75 e .050 BSC 1.27 BSC A1 .004 .010 0.10 0.25 E .150 .157 3.80 4.00 b .014 .019 0.35 0.49 E1 .228 .244 5.80 6.20 c .007 .010 0.19 0.25 L .016 .050 0.40 1.27 D .386 .394 9.80 10.00 NOTES: 1. D and E do not include mold flash. 2. Mold flash or protrusions not to exceed

39、0.15 mm (.006”). 3. Leads to be coplanar within 0.10 mm (.004”). 4. Meets JEDEC MS012-AC. 5. Controlling dimensions are millimeters. Inch dimensions are provide for reference only. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,

40、-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09632 REV PAGE 9 Case outline X Terminal number Terminal symbol FUNCTION 1 VBATT Battery-Backup Input. Connect to external battery or capacitor and charging circuit. If backup battery is not used, connect to GN

41、D. 2 VOUT Output Supply Voltage. When VCC is greater than VBATT and above the reset threshold, VOUT connects to VCC. When VCCfalls below VBATT and is below the reset threshold, VOUT connects to VBATT. Connect a 0.1Fcapacitor from VOUT to GND. Connect VOUT to VCCif no backup battery is used. 3 VCC In

42、put Supply Voltage, 5V Input. 4 GND Ground. 0V reference for all signals. 5 BATT ON Battery-On Output. When VOUT switches to VBATT, BATT ON goes high. When VOUT switches to VCC, BATT ON goes low. Connect the base of a PNP through a current-limiting resistor to BATT ON for VOUT current requirements g

43、reater than 250mA. 6 LOWLINE LOWLINE output goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset threshold. 7 OSC IN External Oscillator Input. When OSC SEL is unconnected or driven high, a 10A pull-up connects from VOUT to OSC IN, the internal osci

44、llator sets the reset and watchdog timeout periods, and OSC IN selects between fast and slow watchdog timeout periods. When OSC SEL is driven low, the reset and watchdog timeout periods may be set either by a capacitor from OSC IN to ground or by an external clock at OSC IN. 8 OSC SEL Oscillator Sel

45、ect. When OSC SEL is unconnected or driven high, the internal oscillator sets the reset delay and watchdog timeout period. When OSC SEL is low, the external oscillator input (OSC IN) is enabled. OSC SEL has a 10A internal pull-up. 9 PFI Power-Fail Input. This is the noninverting input to the power-f

46、ail comparator. When PFI is less than 1.25V, PFO goes low. When PFI is not used, connect PFI to GND or VOUT. 10 PFO Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V. This is an uncommitted comparator, and has no effect on any other internal

47、 circuitry. 11 WDI Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog timeout period. WDO goes low and reset is asserted for the reset timeout period. WDO remains low until the next transition at WDI. Leaving WDI unconnected disables the watchd

48、og function. WDI connects to an internal voltage divider between VOUT and GND, which sets it to mid-supply when left unconnected. 12 CE OUT Chip-Enable Output. CE OUT goes low only when CE IN is low and VCC is above the reset threshold. If CE IN is low when reset is asserted, CE OUT will stay low for 15 s or until CE IN goes high, whichever occurs first. 13 CE