DLA DSCC-VID-V62 03613 REV B-2012 MICROCIRCUIT DIGITAL CMOS 16-BIT DIGITAL SIGNAL PROCESSOR MONOLITHIC SILICON.pdf

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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Add device type 02. Update boilerplate. Editorial changes throughout. - phn 06-02-22 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 12-03-22 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND A

2、ND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV B B B B B B B B PAGE 18 19 20 21 22 23 24 25 REV STATUS OF PAGES REV B B B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Charles F. Saffle

3、DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Original date of drawing CHECKED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, CMOS, 16-BIT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON 02-12-16 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03613 REV B PAGE 1 OF 25 AMSC N/A 5962

4、-V041-12 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03613 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performa

5、nce 16-bit Digital Signal Processor microcircuit, with an operating temperature range of -55C to +125C and of -40C to +80C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number

6、 for identifying the item on the engineering documentation: V62/03613 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SM320C50-66EP 16-bit Digital Signal Processor 02 SM320C50-80EP 16-bit D

7、igital Signal Processor 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 132 JEDEC MO-069 Plastic Quad Flatpack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device m

8、anufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range (VDD) . -0.3 V to +7.0 V 2/ Input voltage range (VI) . -0.3 V to +7.0 V Output voltage range (VO) . -0.3 V to +7.0 V Op

9、erating case temperature range (TC) -55C to +125C Storage temperature range (TSTG) . -65C to +150C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other con

10、ditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltage values are with respect to VSS. Provided by IHSNot for ResaleNo reproduction or networking permitte

11、d without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03613 REV B PAGE 3 1.4 Recommended operating conditions. 1/ Supply voltage range (VDD) . +4.75 V to +5.25 V Supply voltage (VSS) 0 V NOM High level input voltage range (VIH): CLKIN,

12、CLKIN2 . +3.0 V to VDD+0.3 V CLKX, CLKR, TCLKX, TCLKR +2.5 V to VDD+0.3 V All others . +2.2 V to VDD+0.3 V Low level input voltage range (VIL) -0.3 V to +0.6 V Maximum high level output current (IOH) . -300 A 2/ Maximum low level output current (IOL) . +2 mA Operating case temperature range (TC): De

13、vice type 01 . -55C to +125C 3/ Device type 02 . -40C to +85C 3/ 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State

14、Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE) IEEE Standard 1149.1 - IEEE Standard Test Access Port and Boundary Scan Architecture. (Copies of these documents are available online at http:/www.ieee.org o

15、r from the IEEE Service Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 088551331. 1/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the

16、 stated limits. 2/ This IOHcan be exceeded when using a 1-k pulldown resistor on the TDM serial port TADD output; however, this output still meets VOHspecifications under these conditions. 3/ TCMAX at maximum rated operating conditions at any point on case. TCMIN at initial (time zero) power up. Pro

17、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03613 REV B PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers p

18、art number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical cha

19、racteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1

20、 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Block diagram. The block diagram shall be as shown in figure 2. 3.5.3 Terminal connections. The terminal connections shall be as shown in figure 3. 3.5.4 Timing waveforms and test circuit. The timing waveforms and t

21、est circuit shall be as shown in figures 4a 4q. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03613 REV B PAGE 5 TABLE I. Electrical performance characteristics.

22、 1/ Test Symbol Test conditions 4.75 V VDD 5.25 V -55C TC +125C 2/ -45C TC +80C 3/ unless otherwise specified Limits Unit Min Max High level output voltage VOH 4/ IOH= MAX 5/ See figure 4a. 2.4 V Low level output voltage VOL 6/ IOL= MAX 5/ 0.6 V High-impedance output current (VDD= MAX) IOZBR (with i

23、nternal pullup) -500 30 A All others -30 30 Input current (VIN= VSSto VDD) IITRST (with internal pulldown) -30 800 A TMS, TCK, TDI (with Internal pullups) -500 30 X2/CLKIN -50 50 All other inputs -30 30 Supply current, core CPU IDDCOperating, fx= 66 MHz, VDD= 5.25 V, TA= 25C 7/ 225 mA Supply current

24、, pins IDDP225Supply current standby IDDIDLE instruction, fx= 66 MHz, VDD= 5.25 V, TC= 125C 30 mA IDLE2 instruction, Clocks shut off VDD= 5.25 V, TC= 125C 7 A Input capacitance Ci40 pF Output capacitance Co40 pF Internal Divide-by-two Clock Option Input clock frequency fx0 8/ 66 MHz Load capacitance

25、 C1, C2 See figure 4b. 10 Typ pF External Divide-by-two Clock Option Switching Characteristics H = 0.5tc(CO) Cycle time, CLKOUT1 tc(CO)See figure 4c. 30 9/ ns Delay time, X2/CLKIN high to CLKOUT1 high/low td(CIH-COH/L)3 20Fall time, CLKOUT1 tf(CO)5 TypRise time, CLKOUT1 tr(CO)Typ Pulse duration, CLK

26、OUT1 low tw(COL)H3 H+2 Pulse duration, CLKOUT1 high tw(COH)See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03613 REV B PAGE 6 TABLE

27、I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 4.75 V VDD 5.25 V -55C TC +125C 2/ -45C TC +80C 3/ unless otherwise specified Limits Unit Min Max External Divide-by-two Clock Option Timing Requirements Cycle time, X2/CLKIN tc(CI)See figure 4c. 15 9/ ns Fall time

28、, X2/CLKIN tf(CI)5 10/ ns Rise time, X2/CLKIN tr(CI)5 10/ ns Pulse duration, X2/CLKIN low tw(CIL)7 9/ ns Pulse duration, X2/CLKIN high tw(CIH)ns External Divide-by-one Clock Option Switching Characteristics H = 0.5tc(CO)Cycle time, CLKOUT1 tc(CO)See figure 4c 30 75 10/ ns Delay time, CLKIN2 high to

29、CLKOUT1 high td(C2H-COH)2 16Fall time, CLKOUT1 tf(CO)5 Typ ns Rise time, CLKOUT1 tr(CO)TypPulse duration, CLKOUT1 low tw(COL)H3 10/ H+2 10/ ns Pulse duration, CLKOUT1 high tw(COH)H3 10/ H+2 10/ ns Delay time, transitory phase PLL synchronized after CLKIN2 supplied td(TP)1000tc(C2)10/ ns External Div

30、ide-by-one Clock Option Timing Requirements Cycle time, CLKIN2 tc(C2)30 75 11/ ns Fall time, CLKIN2 tf(C2)5 10/ Rise time, CLKIN2 tr(C2)5 10/ Pulse duration, CLKIN2 low tw(C2L)9 tc(C2)- 9 Pulse duration, CLKIN2 high tw(C2H)9 tc(C2)- 9 Memory and Parallel I/O Interface Read Switching Characteristics

31、H = 0.5tc(CO) Setup time, address valid before RD low tsu(AV-RDL)See figure 4e. H-10 12/ 13/ ns Hold time, address valid after RD high th(RDH-AV)0 12/ 13/ Pulse duration, RD low tw(RDL)H2 10/ 14/ Pulse duration, RD high tw(RDH)H2 10/ 14/ Delay time, RD high to WE low td(RDH-WEL)2H-5Memory and Parall

32、el I/O Interface Read Timing Requirements H = 0.5tc(CO) Access time, read data valid from address valid ta(RDAV)See figure 4e. 2H-15 13/ ns Access time, read data valid after RD low ta(RDL-RD)H-10Setup time, read data valid before RD high tsu(RD-RDH)10Hold time, read data valid after RD high th(RDH-

33、RD)0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03613 REV B PAGE 7 TABLE I. Electrical performance characteristics - Continued.

34、 Test Symbol Test conditions4.75 V VDD 5.25 V -55C TC +125C 2/ -45C TC +80C 3/ unless otherwise specified Limits Unit Min Max Memory and Parallel I/O Interface Write Switching Characteristics H = 0.5tc(CO) Setup time, address valid before WE low tsu(AV-WEL)H-5 12/ 13/ ns Hold time, address valid aft

35、er WE high th(WEH-AV)H-10 12/ 13/ ns Pulse duration, WE low tw(WEL)2H-4 10/ 15/ 2H+2 10/ 15/ ns Pulse duration, WE high tw(WEH)2H-2 15/ ns Delay time, WE high to RD low td(WEH-RDL)3H-10 ns Setup time, write data valid before WE high tsu(WDV-WEH)2H-20 10/ 15/ 2H 10/ 15/ 16/ ns Hold time, write data v

36、alid after WE high th(WEH-WDV)H-5 10/ 15/ H+10 10/ 15/ ns Enable time, WE to data bus driven ten(WE-Bud)-5 10/ ns Ready Timing for Externally Generated Wait States Timing Requirements H = 0.5tc(CO) Setup time, READY before CLKOUT1 rises tsu(RY-COH)See figure 4g. 10 ns Hold time, READY after CLKOUT1

37、rises th(CO-RYH)0 Setup time, READY before RD falls tsu(RY-RDL)10 ns Hold time, READY after RD falls th(RDL-RY)Valid time, READY after WE falls tv(WEL-RY)H-15 ns Hold time, READY after WE falls th(WEL-RY)H+5 Reset, Interrupt, and BIO Timing Requirements H = 0.5tc(CO)Setup time, 1INT - 4INT , NMI, be

38、fore CLKOUT1 low 14/tsu(IN-COL)See figure 4h. 15 ns Hold time, 1INT - 4INT , NMI, after CLKOUT1 low 14/th(COL-IN)0 Pulse duration 1INT - 4INT , NMI low, synchronous tw(INL)SYN4H+15 18/ ns Pulse duration, 1INT - 4INT , NMI high, synchronous tw(INH)SYN2H+15 10/ 18/ ns Pulse duration, 1INT - 4INT , NMI

39、 low, asynchronous tw(INL)ASY6H+15 10/ 18/ ns Pulse duration, 1INT - 4INT , NMI high, asynchronous tw(INH)ASY4H+15 10/ 18/ ns Setup time, RS before X2/CLKIN low tsu(RS-X2L)10 ns Pulse duration, RS low tw(RSL)12HDelay time, RS high to reset vector fetch td(RSH)34H ns Pulse duration, BIO low, synchron

40、ous tw(BIL)SYN15Pulse duration, BIO low, asynchronous tw(BIL)ASYH+15 10/ ns Setup time, BIO before CLKOUT1 low tsu(BI-COL)15 ns Hold time, BIO after CLKOUT1 low th(COL-BI)0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-

41、,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03613 REV B PAGE 8 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions 4.75 V VDD 5.25 V -55C TC +125C 2/ -45C TC +80C 3/ unless otherwise specified Limits Unit Min Max Instr

42、uction Acquisition (IAQ), Interrupt Acknowledge (IACK), External Flag(XF) and TOUT Switching Characteristics H = 0.5tc(CO) Setup time, address valid before IAQ low 19/ tsu(AV-IQL)See figure 4i. H-12 20/ ns Hold time, address valid after IAQ low th(IQL-AV)H-10 20/ ns Pulse duration, IAQ low tw(IQL)H-

43、10 20/ ns Delay time, CLKOUT1 falling to TOUT td(CO-TU)-6 6 ns Setup time, address valid before IACK low 21/ tsu(AV-IKL)H-12 20/ ns Hold time, address valid after IAQ high 21/ th(IKH-AV)H-10 20/ ns Pulse duration, IAQ low tw(IKL)H-10 20/ ns Pulse duration, TOUT high tw(TUH)2H-12 ns Delay time, XF va

44、lid after CLKOUT1 td(CO-XFV)0 12External DMA Timing Switching Characteristics H = 0.5tc(CO) 22/ Delay time, HOLD low to HOLDA low td(HOL-HAL)See figure 4j. 4H 23/ ns Delay time, HOLD high before HOLDA high td(HOH-HAH)2HDisable time, address in the high- impedance state before HOLDA low tdis(AZ-HAL)H

45、-15 10/ 24/ ns Enable time, HOLDA high to address driven ten(HAH-Ad)H-5 10/ ns Delay time, XBR low to IAQ low td(XBL-IQL)4H 10/ 6H 10/ ns Delay time, XBR high to IAQ high td(XBH-IQH)2H 10/ 4H 10/ ns Delay time, read data valid after XSTRB low td(XSL-RDV)40Hold time, read data after XSTRB high th(XSH

46、-RD)0 ns Enable time, IAQ low to read data driven ten(IQL-RDd)0 10/ 25/ 2H 10/ ns Disable time, XR/ W low to data in the high-impedance state tdis(W)0 10/ 15 10/ ns Disable time, IAQ high to data in the high-impedance state tdis(I-D)H 10/ ns Enable time, data from XR/ W going high ten(D-XRH)4 10/ ns

47、 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03613 REV B PAGE 9 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions4.75 V VDD 5.25 V -55C TC +125C 2/ -45C TC +80C 3/ unless otherwise specified Limits Unit Min Max External DMA Timing, Timing Requirements 22/ Delay time, HOLDA low to XBR low td(HAL-XBL)See figure 4j. 0 26/ ns Delay time, IAQ low to XSTRB lo