BS IEC 62526-2007 Standard for extensions to standard test interface language (STIL) for semiconductor design environments《半导体设计环境用标准测试接口语言(STIL)的扩展标准》.pdf

《BS IEC 62526-2007 Standard for extensions to standard test interface language (STIL) for semiconductor design environments《半导体设计环境用标准测试接口语言(STIL)的扩展标准》.pdf》由会员分享，可在线阅读，更多相关《BS IEC 62526-2007 Standard for extensions to standard test interface language (STIL) for semiconductor design environments《半导体设计环境用标准测试接口语言(STIL)的扩展标准》.pdf（124页珍藏版）》请在麦多课文档分享上搜索。

1、BRITISH STANDARDBS IEC 62526:2007Standard for Extensions to Standard Test Interface Language (STIL) for Semiconductor Design EnvironmentsICS 25.040.01; 35.060g49g50g3g38g50g51g60g44g49g42g3g58g44g55g43g50g56g55g3g37g54g44g3g51g40g53g48g44g54g54g44g50g49g3g40g59g38g40g51g55g3g36g54g3g51g40g53g48g44g5

2、5g55g40g39g3g37g60g3g38g50g51g60g53g44g42g43g55g3g47g36g58BS IEC 62526:2007This British Standard was published under the authority of the Standards Policy and Strategy Committee on 31 December 2007 BSI 2007ISBN 978 0 580 59314 7National forewordThis British Standard is the UK implementation of IEC 6

3、2526:2007.The UK participation in its preparation was entrusted to Technical Committee GEL/93, Design automation.A list of organizations represented on this committee can be obtained on request to its secretary.This publication does not purport to include all the necessary provisions of a contract.

4、Users are responsible for its correct application.Compliance with a British Standard cannot confer immunity from legal obligations. Amendments issued since publicationAmd. No. Date CommentsIEC 62526Edition 1.0 2007-11INTERNATIONAL STANDARD Standard for Extensions to Standard Test Interface Language

5、(STIL) for Semiconductor Design Environments IEEE 1450.1BS IEC 62526:2007IEEE 1450.1-20051. Overview71.1 Scope.81.2 Purpose92. Definitions, acronyms, and abbreviations.92.1 Definitions 92.2 Acronyms and abbreviations 103. Structure of this standard . 104. STIL syntax description114.1 Reserved words.

6、114.2 Reserved characters 124.3 Reserved UserFunctions .134.4 Signal and group name characteristics144.5 STIL name spaces and name resolution .145. Expressions .155.1 Constant and variable expressions 155.2 Expression delimiterssingle quotes and parentheses 155.3 Arithmetic expressionsinteger, real,

7、 time, boolean 175.4 Pattern data expressions. 185.5 Expression processing.195.6 Booleanboolean_expr 245.7 Integersinteger_expr 245.8 Logic expressionslogic_expr .255.9 Real expressionsreal_expr . 265.10 Addition to timing expressionstime_expr 275.11 SignalVariablessigvar_expr . 285.12 Formal parame

8、ters in procedures and macros . 305.13 Integer listsinteger_list. 306. Statement structure and organization of STIL information . 317. STIL statement. 317.1 STIL syntax 327.2 STIL example 328. UserKeywords statement . 328.1 UserKeywords syntax 328.2 UserKeywords example. 32IEEE Introduction .6CONTEN

9、TSBS IEC 62526:2007IEEE 1450.1-2005 2 9. Variables block 339.1 Variables block syntax. 339.2 Variables example 359.3 Variables scoping. 359.4 Variables synchronizing 3710. Signals block 3810.1 Signals block syntax 3810.2 Signals example . 3810.3 Bracketed signal notation enhancement 3811. SignalGrou

10、ps block 4111.1 SignalGroups syntax 4111.2 SignalGroups, WFCMap, and Variables example. 4111.3 Default WFCMap attribute value 4211.4 Defining indexed signal groups .4212. PatternBurst block 4312.1 PatternBurst syntax 4312.2 PatternBurst example. 4512.3 Tiling and synchronization of patterns 4612.4 I

11、f and While statements . 4813. Timing block and WaveformTable block 4913.1 Additional domain specification 4913.2 CompareSubstitute operations, S. 4914. ScanStructures block 5014.1 ScanStructures syntax 5014.2 Scan cell namingcell_ref, chain_ref, cell_group, chain_group . 5314.3 Scoping rules for Sc

12、anStructure blocks . 5414.4 Example indexed list of scan cells . 5514.5 Example of ScanChainGroups and ActiveScanChain . 5514.6 Scan chain segments and cell groups. 5715. Pattern data 5815.1 Data content read backC, D, E, S, U, W . 5915.2 Vector data mapping and joiningm, j 6115.3 Specifying event d

13、ata in a patterne. 6315.4 Using expressions within pattern data . 6416. Pattern statements 6516.1 Additional Pattern syntax. 6616.2 Vector data constraintsF, E 6716.3 Shift and LoopData statements .6816.4 Loop statement using an integer expression 7016.5 MergedScan function. 71BS IEC 62526:2007IEEE

14、1450.1-2005 3 17. Procedure and macro data substitution 7117.1 Nested procedure and macro cells . 7117.2 Passing parameters to variables . 7217.3 Default value of formal parameters . 7317.4 Data substitution using WFCConstant and SignalVariable. 7318. Environment block. 7518.1 Environment syntax . 7

15、518.2 MAP_STRING syntax. 7718.3 NameMaps example 7718.4 Compact scan-cell mapping using InheritNameMap. 7919. Pragma block . 8019.1 Pragma syntax 8020. PatternFailReport . 8020.1 PatternFailReport syntax 8120.2 PatternFailReport example 82Annex A (informative) Glossary . 82Annex B (informative) Sign

16、al mapping using SignalVariables. 85Annex C (informative) Using logic expression with signals . 89Annex D (informative) Using boolean expressions in patterns. 90Annex E (informative) Variables and expressions in algorithmic patterns 91Annex F (informative) Using AllowInterleave 93Annex G (informativ

17、e) Vector data mapping using m 96Annex H (informative) Vector data joining using j .99Annex I (informative) Block data collection 102Annex J (informative) Using Fixed and Equivalent statements .104Annex K (informative) Independent parallel patterns . 106Annex L (informative) Applications using new S

18、canStructures syntax 108Annex M (informative) BreakPoints using MergedScan() function 112Annex N (informative) Labels and X statements for diagnostic feedback 115Annex O (informative) Use of STIL.1 for specific applications . 118Annex P (informative) Bibliography . 120Annex Q (informative) List of p

19、articipants . 121BS IEC 62526:2007IEEE 1450.1-2005 4 IEEE Standard for Extensions toStandard Test Interface Language (STIL)(IEEE Std 1450TM-1999) for SemiconductorDesign EnvironmentsSponsorTest Technology Standards Committeeof theIEEE Computer SocietyApproved 9 June 2005IEEE-SA Standards BoardAbstra

20、ct: Standard Test Interface Language (STIL) provides an interface between digital testgeneration tools and test equipment. Extensions to the test interface language (contained in thisstandard) are defined that (1) facilitate the use of the language in the design environment and(2) facilitate the use

21、 of the language for large designs encompassing subdesigns with reusablepatterns.Keywords: advanced scan architecture, core, environment, fail feedback, lockstep, parallelpatterns, parameterized data, pattern tiling, pragma, signal variable, system on chip (SoC), testprotocolBS IEC 62526:2007IEEE 14

22、50.1-2005 5 IEEE IntroductionThe Standard Test Interface Language (STIL) was initially developed by an ad hoc consortium of automatictest equipment vendors (ATE), electronic design automation vendors (EDA), and integrated circuit (IC)manufacturers to address the lack of a common solution for transfe

23、rring digital test data from the generationenvironment to the test equipment.The scope of the initial STIL standard was limited to satisfy the basic needs of pattern definition. Additionalcapabilities are developed as separate projects resulting in separate (dot) extensions to the initial STILstanda

24、rd. The scope of this extension is defined in 1.1 and is primarily to address design needs.Whereas the initial STIL standard was developed by reviewing many languages already in existence in theindustry, this standard has been developed by inventing new capabilities in support of new device designs.

25、The new language constructs have been added such that they do not alter in any way the initial definition ofSTIL, yet are syntactically compatible with the initial STIL language.Much of the work to develop and validate these extensions has been done by prototyping on the part of thecontributing comp

26、anies.Notice to usersErrataErrata, if any, for this and all other standards can be accessed at the following URL: http:/standards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL forerrata periodically.InterpretationsCurrent interpretations can be accessed at t

27、he following URL: http:/standards.ieee.org/reading/ieee/interp/index.html.PatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence

28、orvalidity of any patent rights in connection therewith. The IEEE shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are brought to

29、its attention.BS IEC 62526:2007IEEE 1450.1-2005 6 STANDARD FOR EXTENSIONS TOSTANDARD TEST INTERFACE LANGUAGE (STIL)(IEEE Std 1450TM-1999) FOR SEMICONDUCTORDESIGN ENVIRONMENTS1. OverviewSTIL is an evolving standard being developed in support of various needs for interfacing between testgeneration too

30、ls and test equipment. IEEE Std 1450-1999 (STIL.0) B31forms the basis for this evolution.New “dot” standards (like this one) are being developed to address specific needs beyond STIL.0.This (STIL.1) standard addresses design-related aspects of digital test data. This standard can also be viewedas th

31、e addition of advanced features to the STIL.0 baseline to allow for the usage of STIL in more complexapplications, while leaving the basic standard unchanged as a vehicle for transmitting basic test data. Thefollowing is a brief overview of the new features in STIL.1 to support advanced applications

32、 such as(1) embedded cores,2(2) families of test patterns, (3) mapping to automated test equipment (ATE) systems,3(4) mapping to simulation, and (5) devices with advanced design for test (DFT). Please see Annex O for alist of specific statements for each of these features.Environment mapping: Data f

33、or a device exist in many forms and in many other software environments.Examples include (1) simulation environment, (2) static analysis environment, (3) specific ATE systemenvironment. The STIL Environment block is a new mechanism to relate STIL data to these otherenvironments. No assumptions, expe

34、ctations, or limitations are imposed on the other environments. It is justa way of relating one to the other.Parameterized data: Much of STIL data are declarative in nature (i.e., it defines various static attributes of adevice or pattern set). The addition of constant declarations, IntegerConstant

35、and WFCConstant, allows adata set to be created that applies to a family of devices.Complex test protocol definition: Test protocol definitions are usually contained in STIL procedures orMacroDefs and are used to specify the application of a series of data values to a device. STIL.0 supportsscan cha

36、in data passing and simple WaveformCharacter (WFC) data passing via the # and % characters.STIL.1 enhances this capability by allowing the use of data substitution from SignalVariables and integer-1The numbers in brackets correspond to those of the bibliography in Annex P.2This standard contains syn

37、tax in support of embedded cores. See IEEE Std 1450.6TM-2005 (Core Test Language) B5 for the complete specification.3This standard contains syntax in support of ATE systems. See IEEE P1450.3TM(Test Resource Constraints) B4 for the complete specification.BS IEC 62526:2007IEEE 1450.1-2005 7 Complex te

38、st protocol definition: Test protocol definitions are usually contained in STIL procedures orMacroDefs and are used to specify the application of a series of data values to a device. STIL.0 supportsscan chain data passing and simple WaveformCharacter (WFC) data passing via the # and % characters.STI

39、L.1 enhances this capability by allowing the use of data substitution from SignalVariables and integer-expressions. STIL.1 also enhances the functionality of Loops and Vectors and adds If/While decisions onpattern statements. These capabilities are needed for BIST, embedded cores, and various test a

40、ccessmechanisms.Advanced scan architecture: Advanced DFT techniques require additional capabilities beyond what isdefined in STIL.0, which includes multistate scan cells, reconfigurable scan-chains, and scan-chainindexing.Run-time pattern decisions: The If, Else, While, and LoopData are new STIL.1 c

41、onstructs that have beenadded for specification of pattern activity. These statements are needed in the specification of patterns to berun in the simulation environment. Although there is no standardization among ATE systems on run-timeinstructions for pattern execution, it is anticipated that restr

42、icted versions of these statements will beincorporated into ATE test patterns. Pattern burst options: New variations on the PatternBurst have been added to allow for patterns running inparallel, patterns running in LockStep, and patterns that can be reordered. For parallel pattern execution, thespec

43、ification for how the patterns fit together can be specified with the Fixed and Extend statements.Enhanced user extensibility: The UserKeyword extensibility defined in STIL.0 has been extended to allowkeywords to be defined on a per-block-type basis.Signal relationships: Additional syntax is provide

44、d to allow the specification of relationships betweensignals. This process is preformed via m to map WFCs to another WFC, j to join WFCs, Extend to definebehavior of signals beyond the bounds of a given pattern, and Fixed to restrict any further changes to signalswithin a pattern.Fail feedback: Thre

45、e new features are added to facilitate the processing of failure data from an ATE systemback to design tools. The first is the X or cross-reference statement that allows the specification of where ina pattern/vector sequence a failure occurs. The second is the FailFeedback block for reporting fails.

46、 Thethird is the S/s timing event that allows for the specification of a data capture protocol for the purpose ofcapturing bulk fail data for processing.1.1 ScopeStructures are defined in STIL to support usage as semiconductor simulation stimulus, including(1) mapping signal names to equivalent desi

47、gn references, (2) interface between scan and built-in self test(BIST) and the logic simulation, (3) data types to represent unresolved states in a pattern, (4) parallel orasynchronous pattern execution on different design blocks, and (5) expression-based conditional executionof pattern constructs.S

48、tructures are defined in STIL to support the definition of test patterns for sub-blocks of a design4(i.e., embedded cores) such that these tests can be incorporated into a complete higher level device test.Structures are defined in STIL to relate fail information from device testing environments bac

49、k to originalstimulus and design data elements.4Syntax in this document that is used in the definition of patterns for sub-blocks is summarized in Annex O.BS IEC 62526:2007IEEE 1450.1-2005 8 1.2 PurposeThe STIL language definition is enhanced to support the usage of STIL in the design environment, whichincludes extending the execution concept to support STIL as a stimulus language, to allow STIL to be usedas an intermediate form of data, and to allow STIL to capture design information needed to port simulationdata to device test environments.