ANSI IEEE 1445-2016 Standard for Digital Test Interchange Format (DTIF).pdf
《ANSI IEEE 1445-2016 Standard for Digital Test Interchange Format (DTIF).pdf》由会员分享,可在线阅读,更多相关《ANSI IEEE 1445-2016 Standard for Digital Test Interchange Format (DTIF).pdf(64页珍藏版)》请在麦多课文档分享上搜索。
1、IEEE Standard for Digital Test Interchange Format (DTIF)IEEE Std 1445-2016(Revision of IEEE Std 1445-1998)IEEE-SA Standards BoardSponsored by the Standards Coordinating Committee 20 (SCC20)IEEE3 Park AvenueNew York, NY 10016-5997USAIEEE Std 1445-2016(Revision of IEEE Std 1445-1998)IEEE Standard for
2、Digital Test Interchange Format (DTIF)Sponsor Standards Coordinating Committee 20 (SCC20) of the IEEE-SA Standards BoardApproved 7 December 2016IEEE-SA Standards BoardAbstract: The information content and the data formats for the interchange of digital test pro-gram data between digital automated te
3、st program generators (DATPGs) and automatic test equip-PHQW $7( IRUERDUGOHYHOSULQWHGFLUFXLWDVVHPEOLHVDUHGHQHG7KLVLQIRUPDWLRQFDQEHEURDGOJURXSHGLQWRGDWDWKDWGHQHVWKHIROORZLQJXVHUXQGHUWHVW 887 PRGHOVWLPXOXVDQGUHVSRQVHIDXOWGLFWLRQDUDQGSUREHKeywords:DXWRPDWLFWHVWHTXLSPHQW$7($73*GLJLWDODXWRPDWHGWHVWSURJUD
4、PJHQHUDWRUGLJLWDOWHVWLQWHUFKDQJHIRUPDW7,)IDXOWGLFWLRQDUGDWD,(7KH,QVWLWXWHRI(OHFWULFDODQG(OHFWURQLFV(QJLQHHUV,QF3DUN$YHQXH1HZ6 SA 1 (component: U5, SLQIDXOWWSH6WXFNDW go/nogo test: See: end-to-end test.LASAR 4: Simulation software, used for digital test program set (TPS) development. LASARpredicts th
5、e timing variability of signals and the behavior of the unit under test (UUT) when a physical or logic fault is present. LASAR builds an accurate diagnostic database for isolating faults on the UUT. LASAR also SUHGLFWVWKHHIIHFWRIWKHWHVWWXUHRQWKH887ZRUVWFDVHWLPLQJSUREOHPVDQGFRPSDWLELOLWZLWKWKHWDUJHWt
6、ester. The name LASAR is an acronym for “logic automated stimulus and response.”logic state: The representation a simulator uses to describe the state of a circuit during digital logic simulation. There are four types of logic states that exist in a typical simulator: 0, 1, Z, and X.main model7KHWRS
7、OHYHOXQLWXQGHUWHVW 887 PRGHOGHVFULSWLRQWKDWLQFOXGHVDOLVWRIFRPSRQHQWSDFNDJ-es and a -list: A point-to-point description of the interconnections between individual components in a circuit.packet$JURXSRISRLQWHUVLQDOH7KHJURXSVRISRLQWHUVDUHXVHGWRSURYLGHFKLSSLQLQIRUPDWLRQZLWKRWKHUSLQUHODWHGGDWDOHVpatterns
8、: A set of unit under test (UUT) stimulus and expected response states. A pattern contains one unit of logic state (0, 1, X, Z) data for each UUT input and each UUT output pin.phase: The time within a timing cycle when a primary input is in transition between logic states.4/$6$5LVDWUDGHPDUNRI7HUDGQH
9、,QFIEEE Std 1445-2016,(6WDQGDUGIRULJLWDO7HVW,QWHUFKDQJH)RUPDW 7,) 13OHVZKLFKLQFOXGHVDKHDGHUOHDQGGDWDOHV57KHKHDGHUOHSURYLGHVVXPPDULQIRUPDWLRQDQGDOLVWLQJEQDPHRIWKH7,)OHVHWJHQHUDWHGEDVLPX-ODWRUIRUDJLYHQGLJLWDOFLUFXLW QRWDOO7,)OHVDUHUHTXLUHGWREHLQWKHGDWDVHW 7KHUHPDLQLQJ7,)GDWDOHVDUHRUJDQLHGLQWRWKHIRXUIX
10、QFWLRQDOJURXSV7KLVRUJDQLDWLRQSRUWUDVWKHrole of each functional group as it relates to UUT testing. They are: 8870RGHO*URXS GDWDOHV 6WLPXOXVDQG5HVSRQVH*URXS QLQHGDWDOHV )DXOWLFWLRQDU*URXS VLGDWDOHV 3UREH*URXS HLJKWGDWDOHV 7KH8870RGHO*URXSFRQWDLQVDOOWKHOHVUHTXLUHGWRGHQHWKHWRSRORJLFDOGDWDEDVHIRUGLDJQRV
11、LQJIDXOWVon the UUT. This includes component instantiations, component input/output (I/O) pins, primary inputs, pri-PDURXWSXWVDQGSDFNDJHLQWHUFRQQHFWLRQV7KH6WLPXOXVDQG5HVSRQVH*URXSFRQWDLQVDOOWKHOHVUHTXLUHGIRUIDXOWGHWHFWLRQWHVWLQJ HQGWRHQG 7KHintent of an end-to-end test of a UUT is to verify the over
12、all functionality of the item and to indicate a failure if one exists and can be detected by the test pattern set developed for it. There is no explicit attempt to diagnose the cause of the failure.5Information on references can be found in Clause 2.IEEE Std 1445-2016,(6WDQGDUGIRULJLWDO7HVW,QWHUFKDQ
13、JH)RUPDW 7,) 15,/,$5B3,1B1$0(6 auxpins.tapNODE_NAMES nodenames.tap4.2 Stimulus and response group7KH6WLPXOXVDQG5HVSRQVH*URXSFRQVLVWVRIQLQHGDWDOHWSHVWKDWGHQHWKHORJLFYDOXHRIDSSOLHGVWLPX-OXVDQGREVHUYHGJRRGFLUFXLWUHVSRQVH7KHVHGDWDOHWSHVLGHQWLI The timing of stimulus edge transitions within a pattern The
14、 period of valid output responses within a pattern *URXSVRI887SLQVZLWKWKHVDPHVWLPXOXVDQGUHVSRQVHWLPLQJFKDUDFWHULVWLFV(DFKRIWKHQLQHGDWDOHWSHVKDVDQDVVRFLDWHGOHQDPHTable 2LGHQWLHVHDFKRIWKH7,)OHWSHVDQGLWVDVVRFLDWHG7,)OHQDPH7DEOH6WLPXOXVDQG5HVSRQVH*URXSOHWSHVDQGOHQDPHV7,)OHWSHQDPH 7,)OHQDPHSTIMULUS stimu
- 1.请仔细阅读文档,确保文档完整性,对于不预览、不比对内容而直接下载带来的问题本站不予受理。
- 2.下载的文档,不会出现我们的网址水印。
- 3、该文档所得收入(下载+内容+预览)归上传者、原创作者;如果您是本文档原作者,请点此认领!既往收益都归您。
下载文档到电脑,查找使用更方便
10000 积分 0人已下载
下载 | 加入VIP,交流精品资源 |
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- ANSIIEEE14452016STANDARDFORDIGITALTESTINTERCHANGEFORMATDTIFPDF

链接地址:http://www.mydoc123.com/p-435046.html